[all-commits] [llvm/llvm-project] 918966: [RISCV] RISCV vector calling convention (1/2) (#77...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91896607ffb84561a7a2e466a00fdf1938c5bb63
      https://github.com/llvm/llvm-project/commit/91896607ffb84561a7a2e466a00fdf1938c5bb63
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-03-27 (Wed, 27 Mar 2024)

  Changed paths:
    M clang/include/clang-c/Index.h
    M clang/include/clang/Basic/Attr.td
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/Specifiers.h
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/lib/AST/Type.cpp
    M clang/lib/AST/TypePrinter.cpp
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/CodeGen/CGCall.cpp
    M clang/lib/CodeGen/CGDebugInfo.cpp
    M clang/lib/Sema/SemaDeclAttr.cpp
    M clang/lib/Sema/SemaType.cpp
    A clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
    A clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
    A clang/test/CodeGen/RISCV/riscv-vector-callingconv.c
    A clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
    M clang/tools/libclang/CXType.cpp
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/BinaryFormat/Dwarf.def
    M llvm/include/llvm/IR/CallingConv.h
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/IR/AsmWriter.cpp
    M llvm/lib/Target/RISCV/RISCVCallingConv.td
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    A llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll

  Log Message:
  -----------
  [RISCV] RISCV vector calling convention (1/2) (#77560)

    [RISCV] RISCV vector calling convention (1/2)

    This is the vector calling convention based on
    https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
    the idea is to split between "scalar" callee-saved registers
    and "vector" callee-saved registers. "scalar" ones remain the
    original strategy, however, "vector" ones are handled together
    with RVV objects.

    The stack layout would be:

      |--------------------------| <-- FP
      | callee-allocated save    |
      | area for register varargs|
      |--------------------------|
      | callee-saved registers   | <-- scalar callee-saved
      |        (scalar)          |
      |--------------------------|
      | RVV alignment padding    |
      |--------------------------|
      | callee-saved registers   | <-- vector callee-saved
      |        (vector)          |
      |--------------------------|
      | RVV objects              |
      |--------------------------|
      | padding before RVV       |
      |--------------------------|
      | scalar local variables   |
      |--------------------------| <-- BP
      | variable size objects    |
      |--------------------------| <-- SP

    Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.
          It will be handled in https://github.com/riscv-non-isa/riscv-elf-psabi-doc (2/2).

    Differential Revision: https://reviews.llvm.org/D154576



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