[all-commits] [llvm/llvm-project] ecf6bb: [RISCV] Add register overlap checks to the assembl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecf6bb2b4dbd26bbff2cee79db010369faa2fe90
      https://github.com/llvm/llvm-project/commit/ecf6bb2b4dbd26bbff2cee79db010369faa2fe90
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-26 (Tue, 26 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    A llvm/test/MC/RISCV/rvv/zvkned-invalid.s
    A llvm/test/MC/RISCV/rvv/zvknh-invalid.s
    A llvm/test/MC/RISCV/rvv/zvksed-invalid.s
    A llvm/test/MC/RISCV/rvv/zvksh-invalid.s
    M llvm/test/MC/RISCV/rvv/zvksh.s

  Log Message:
  -----------
  [RISCV] Add register overlap checks to the assembler for some Zvk* instructions. (#86745)

>From the spec

| Instruction | Register | Cannot Overlap |
| ----------- | -------- | -------------- |
| vaes*.vs    | vs2      | vd             |
| vsm4r.vs    | vs2      | vd             |
| vsha2c[hl]  | vs1, vs2 | vd             |
| vsha2ms     | vs1, vs2 | vd             |
| sm3me       | vs2      | vd             |
| vsm3c       | vs2      | vd             |



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