[all-commits] [llvm/llvm-project] 54a9f0: [RISCV][GISEL] Legalize, regbankselect, and instru...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 54a9f0e441c7cc3c954d24cfde00cb933306a9e9
      https://github.com/llvm/llvm-project/commit/54a9f0e441c7cc3c954d24cfde00cb933306a9e9
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-03-26 (Tue, 26 Mar 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir

  Log Message:
  -----------
  [RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (#85967)

G_VSCALE should be lowered using VLENB. If the type is not sXLen it
should be lowered using a G_VSCALE on the narrow type and a G_MUL.
regbank select and instruction select are straightforward so we really
only need to add tests to show it works.



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