[all-commits] [llvm/llvm-project] 87519a: [RISCV] Combine (mul (zext, zext)) -> (zext (mul (...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 87519a2830eab4b634a5816f53fe773929eed531
      https://github.com/llvm/llvm-project/commit/87519a2830eab4b634a5816f53fe773929eed531
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-26 (Tue, 26 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll

  Log Message:
  -----------
  [RISCV] Combine (mul (zext, zext)) -> (zext (mul (zext, zext))) (#86465)

Building on #86248, we can also narrow the width of a mul of zexts.

This is specifically legal because on RVV we always extend to the next
power of 2 width, and multiplying two N bit integers produces a maximum
value of 2\*N bits.
So as long as we keep an inner zext of 2\*N, we will have enough space
for the multiply and won't overflow.

Alive2 proof: https://alive2.llvm.org/ce/z/XteYyb



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