[all-commits] [llvm/llvm-project] a6b870: [RISCV] Enable sub(max, min) lowering for ABDS and...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6b870db091830844431f77eb47aa30fc1d70bed
      https://github.com/llvm/llvm-project/commit/a6b870db091830844431f77eb47aa30fc1d70bed
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-03-25 (Mon, 25 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/abd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll

  Log Message:
  -----------
  [RISCV] Enable sub(max, min) lowering for ABDS and ABDU (#86592)

We have the ISD nodes for representing signed and unsigned absolute
difference. For RISCV, we have vector min/max in the base vector
extension, so we can expand to the sub(max,min) lowering.

We could almost use the default expansion, but since fixed length
min/max are custom (not legal), the default expansion doesn't cover the
fixed vector cases. The expansion here is just a copy of the generic
code specialized to allow the custom min/max nodes to be created so they
can in turn be legalized to the _vl variants.

Existing DAG combines handle the recognition of absolute difference
idioms and conversion into the respective ISD::ABDS and ISD::ABDU nodes.

This change does have the net effect of potentially pushing a free
floating zero/sign extend after the expansion, and we don't do a great
job of folding that into later expressions. However, since in general
narrowing can reduce required work (by reducing LMUL) this seems like
the right general tradeoff.



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