[all-commits] [llvm/llvm-project] 865294: [CodeGen][MISched] Add misched post-regalloc bidir...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 865294b2e67d91d6e6a123db1b71a175e015a210
      https://github.com/llvm/llvm-project/commit/865294b2e67d91d6e6a123db1b71a175e015a210
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-03-25 (Mon, 25 Mar 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/test/CodeGen/RISCV/misched-postra-direction.mir

  Log Message:
  -----------
  [CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)

This PR is stacked on #76186.

This PR keeps the default strategy as top-down since that is what
existing targets expect. It can be enabled using
`-misched-postra-direction=bidirectional`.

It is up to targets to decide whether they would like to enable this
option for themselves.



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