[all-commits] [llvm/llvm-project] e64e15: [RISCV] Move the RISCVSchedule.td include after RI...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e64e15ee597370a9731fcba0b2b8a514f26125e7
      https://github.com/llvm/llvm-project/commit/e64e15ee597370a9731fcba0b2b8a514f26125e7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-22 (Fri, 22 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td

  Log Message:
  -----------
  [RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC

Registers shouldn't depend on the scheduler, but a scheduler
predicate could depend on a register.

This would make it possible to move VLDSX0Pred out of the SiFive7
scheduler model to RISCVSchedule.td if another model needed it.



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