[all-commits] [llvm/llvm-project] 0289ae: [MLIR][LLVM][SROA] Support incorrectly typed memor...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0289ae51aa375fd297f1d03d27ff517223e5e998
      https://github.com/llvm/llvm-project/commit/0289ae51aa375fd297f1d03d27ff517223e5e998
  Author: Christian Ulmann <christianulmann at gmail.com>
  Date:   2024-03-22 (Fri, 22 Mar 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/LLVMIR/Transforms/TypeConsistency.h
    M mlir/include/mlir/Interfaces/MemorySlotInterfaces.h
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
    M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/sroa.mlir
    M mlir/test/Dialect/LLVMIR/type-consistency.mlir

  Log Message:
  -----------
  [MLIR][LLVM][SROA] Support incorrectly typed memory accesses (#85813)

This commit relaxes the assumption of type consistency for LLVM dialect
load and store operations in SROA. Instead, there is now a check that
loads and stores are in the bounds specified by the sub-slot they
access.

This commit additionally removes the corresponding patterns from the
type consistency pass, as they are no longer necessary.

Note: It will be necessary to extend Mem2Reg with the logic for
differently sized accesses as well. This is non-the-less a strict
upgrade for productive flows, as the type consistency pass can produce
invalid IR for some odd cases.



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