[all-commits] [llvm/llvm-project] 51d5b6: [RISCV] Handle scalable ops with < EEW / 2 narrow ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51d5b6581912c8495360a09a0e6be978e0374d90
      https://github.com/llvm/llvm-project/commit/51d5b6581912c8495360a09a0e6be978e0374d90
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-22 (Fri, 22 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

  Log Message:
  -----------
  [RISCV] Handle scalable ops with < EEW / 2 narrow types in combineBinOp_VLToVWBinOp_VL (#84158)

We can remove the restriction that the narrow type needs to be exactly
EEW / 2 for scalable ISD::{ADD,SUB,MUL} nodes. This allows us to perform
the combine even if we can't fully fold the extend into the widening op.

VP intrinsics already do this, since they are lowered to _VL nodes which
don't have this restriction.

The "exactly EEW / 2" narrow type restriction prevented us from emitting
V{S,Z}EXT_VL nodes with i1 element types which crash when we try to
select them, since no other legal type is double the size of i1, see the
test case added in this PR `i1_zext`. So to preserve this, this adds a
check for i1 narrow types instead.



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