[all-commits] [llvm/llvm-project] 07a5e3: Move pre-commit test for #85737 (#86062)

[Vitaly Buka via All-commits]

  Branch: refs/heads/users/vitalybuka/spr/codegen-add-default-lowering-for-llvmallowruntimeubsancheck
  Home:   https://github.com/llvm/llvm-project
  Commit: 07a5e31cb3836bf1f00d2f56f03db70145f536c1
      https://github.com/llvm/llvm-project/commit/07a5e31cb3836bf1f00d2f56f03db70145f536c1
  Author: Freddy Ye <freddy.ye at intel.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    A llvm/test/CodeGen/X86/apx/domain-reassignment.mir
    R llvm/test/CodeGen/X86/domain-reassignment-ndd.mir

  Log Message:
  -----------
  Move pre-commit test for #85737 (#86062)


  Commit: deefe3fbc93b3bdc77fbaf718403a45dae983d12
      https://github.com/llvm/llvm-project/commit/deefe3fbc93b3bdc77fbaf718403a45dae983d12
  Author: Thorsten Schütt <schuett at gmail.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
    M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
    M llvm/test/CodeGen/AArch64/overflow.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll

  Log Message:
  -----------
  [GlobalIsel] Post-review combine ADDO (#85961)

https://github.com/llvm/llvm-project/pull/82927


  Commit: 29bf32efbb646b2ab3dec25f100419fc75635878
      https://github.com/llvm/llvm-project/commit/29bf32efbb646b2ab3dec25f100419fc75635878
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    A llvm/include/llvm/Passes/TargetPassRegistry.inc
    A llvm/lib/Target/AArch64/AArch64PassRegistry.def
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll

  Log Message:
  -----------
  [NewPM][AArch64] Add AArch64PassRegistry.def (#85215)

PR #83567 ports `SelectionDAGISel` to the new pass manager, then each
backend should provide `<Target>DagToDagISel()` in new pass manager
style. Then each target should provide `<Target>PassRegistry.def` to
register backend passes in `registerPassBuilderCallbacks` to reduce
duplicate code.
This PR adds `AArch64PassRegistry.def` to AArch64 backend and
boilerplate code in `registerPassBuilderCallbacks`.


  Commit: 9a3b44439614222a5b09558096e2e08d64c961fa
      https://github.com/llvm/llvm-project/commit/9a3b44439614222a5b09558096e2e08d64c961fa
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    A llvm/include/llvm/Passes/TargetPassRegistry.inc
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    A llvm/lib/Target/AArch64/AArch64PassRegistry.def
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
    M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
    M llvm/test/CodeGen/AArch64/overflow.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    A llvm/test/CodeGen/X86/apx/domain-reassignment.mir
    R llvm/test/CodeGen/X86/domain-reassignment-ndd.mir
    M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]


  Commit: fb91328f57eb4cb461d2d80c6d1b10769cfcb41c
      https://github.com/llvm/llvm-project/commit/fb91328f57eb4cb461d2d80c6d1b10769cfcb41c
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    A llvm/include/llvm/Passes/TargetPassRegistry.inc
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    A llvm/lib/Target/AArch64/AArch64PassRegistry.def
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
    M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
    M llvm/test/CodeGen/AArch64/overflow.ll
    M llvm/test/CodeGen/AMDGPU/allow-check.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/Generic/allow-check.ll
    M llvm/test/CodeGen/RISCV/allow-check.ll
    M llvm/test/CodeGen/X86/allow-check.ll
    A llvm/test/CodeGen/X86/apx/domain-reassignment.mir
    R llvm/test/CodeGen/X86/domain-reassignment-ndd.mir
    M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll

  Log Message:
  -----------
  explicit isel

Created using spr 1.3.4


Compare: https://github.com/llvm/llvm-project/compare/6074de0cf6f4...fb91328f57eb

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