[all-commits] [llvm/llvm-project] f5c90f: [RISCV] Use BuildPairF64 and SplitF64 for bitcast ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5c90f3000bc75a344bf01bd4e0401e3fb7f9453
      https://github.com/llvm/llvm-project/commit/f5c90f3000bc75a344bf01bd4e0401e3fb7f9453
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/spill-fill-fold.ll

  Log Message:
  -----------
  [RISCV] Use BuildPairF64 and SplitF64 for bitcast i64<->f64 on rv32 regardless of Zfa. (#85982)

Previously we used BuildPairF64 and SplitF64 only if Zfa was supported
since they will select register file moves that are only available with
Zfa.

We recently changed the handling of BuildPairF64/SplitF64 for Zdinx to
not go through memory so we should use that for bitcast.

That leaves the D without Zfa case that does need to go through memory.
Previously we let type legalization expand to loads and stores using a
new stack temporary created for each bitcast. After this patch we will
create the loads ands stores in the custom inserter and share the same
stack slot for all. This also allows DAGCombiner to optimize when
bitcast is mixed with BuildPairF64/SplitF64.



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