[all-commits] [llvm/llvm-project] 7e72ca: [SelectionDAG] Add MaskedValueIsZero check to allo...

[AtariDreams via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e72cafd68335e45d95ea6b7705bb5b9e7e442c8
      https://github.com/llvm/llvm-project/commit/7e72cafd68335e45d95ea6b7705bb5b9e7e442c8
  Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
  Date:   2024-03-21 (Thu, 21 Mar 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/dagcombine-shifts.ll

  Log Message:
  -----------
  [SelectionDAG] Add MaskedValueIsZero check to allow folding of zero extended variables we know are safe to extend (#85573)

Add ones for every high bit that will cleared.

This will allow us to evaluate variables that have their bits known to
see if they have no risk of overflow despite the shift amount being
greater than the difference between the two types.



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