[all-commits] [llvm/llvm-project] ce8e86: [RISCV] Convert an assertion to an if condition in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce8e86971036cb34c3d32cf0b70169379c85ae2f
      https://github.com/llvm/llvm-project/commit/ce8e86971036cb34c3d32cf0b70169379c85ae2f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-20 (Wed, 20 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

  Log Message:
  -----------
  [RISCV] Convert an assertion to an if condition in getRegAllocationHints (#85998)

With GPR pairs from Zdinx, we can't guarantee there are no subregisters
on integer instruction operands. I've been able to get these assertions
to fire after some other recent PRs.

I've added a FIXME to support this properly. I just wanted to prevent
the assertion failure for now.

No test case because my other patch #85982 that allowed me to fail the assert
hasn't been approved yet, and I don't know for that that patch is
required to hit this assert. It's just what exposed it for me. So I
think this patch is a good precaution regardless.



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