[all-commits] [llvm/llvm-project] c25e77: Revert "[libomptarget][nextgen-plugin] Use SCRELEA...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Mar 20 10:18:47 PDT 2024
Branch: refs/heads/users/alexey-bataev/spr/slpimprove-minbitwidth-analysis-for-operands-of-itofp-and-icmp
Home: https://github.com/llvm/llvm-project
Commit: c25e77436ea44b4c980f4974dee8984298d13a08
https://github.com/llvm/llvm-project/commit/c25e77436ea44b4c980f4974dee8984298d13a08
Author: Gheorghe-Teodor Bercea <doru.bercea at amd.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M libc/utils/gpu/loader/amdgpu/Loader.cpp
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
Revert "[libomptarget][nextgen-plugin] Use SCRELEASE/SCACQUIRE in packet headers" (#85950)
Reverts llvm/llvm-project#85678
Commit: 767e0c8bcef9cfcc57e76e66e23489ba60042762
https://github.com/llvm/llvm-project/commit/767e0c8bcef9cfcc57e76e66e23489ba60042762
Author: Thomas Lively <tlively at google.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
A llvm/test/CodeGen/WebAssembly/pr63817.ll
Log Message:
-----------
[WebAssembly] Select BUILD_VECTOR with large unsigned lane values (#85880)
Previously we expected lane constants to be in the range of signed
values for each lane size, but the included test case produced large
unsigned values that fall outside that range. Allow instruction
selection to proceed in this case rather than failing.
Fixes #63817.
Commit: 576d81baa5cf1801bae0fd05892be34acde33c6a
https://github.com/llvm/llvm-project/commit/576d81baa5cf1801bae0fd05892be34acde33c6a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-fcmp.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-isnan.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/pr64645.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
Log Message:
-----------
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
Previously we used memory like we do to move between GPRs and FPR64 with
the D extension on RV32.
We can instead use REG_SEQUENCE/EXTRACT_SUBREG to inform register
allocation how to do the copy without memory.
Commit: 3deaa77f1a25f0cdfcf23c34fac0b51293f32f9c
https://github.com/llvm/llvm-project/commit/3deaa77f1a25f0cdfcf23c34fac0b51293f32f9c
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/default-clause-byref.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-rename.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-2-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul.f90
Log Message:
-----------
[flang][OpenMP] simplify getReductionName (#85666)
Re-use fir::getTypeAsString instead of creating something new here. This
spells integer names like i32 instead of i_32 so there is a lot of test
churn.
Commit: 9ebd329ad87ca4cde3ce62e1bf5612c4fc0fcb7f
https://github.com/llvm/llvm-project/commit/9ebd329ad87ca4cde3ce62e1bf5612c4fc0fcb7f
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
M llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/SystemZ/int-cmp-56.mir
M llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
M llvm/test/CodeGen/X86/callbr-asm-kill.mir
M llvm/test/CodeGen/X86/regalloc-copy-hints.mir
M llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
M llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
M llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
M llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
R llvm/test/MachineVerifier/test_adjustsstack.mir
Log Message:
-----------
Revert "Move assertion for AdjustsStack from PEI to MachineVerifier. (#85698)"
This reverts commit 05bde30585710a51592eee0a6cf6df8184d09c92.
Reverting due to verifier complaints with expensive checks on build-bot.
Commit: d209d1340b99d4fbd325dffb5e13b757ab8264ea
https://github.com/llvm/llvm-project/commit/d209d1340b99d4fbd325dffb5e13b757ab8264ea
Author: Martin Storsjö <martin at martin.st>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M libcxx/modules/CMakeLists.txt
Log Message:
-----------
[libcxx] [cmake] Fix cmake_path(ABSOLUTE_PATH) for empty CMAKE_INSTALL_PREFIX
This should hopefully fix the issue brought up at
https://github.com/llvm/llvm-project/pull/85756#issuecomment-2009852291.
Commit: eb861acd49e4c6777e2fe09dd2004ac1f4731bba
https://github.com/llvm/llvm-project/commit/eb861acd49e4c6777e2fe09dd2004ac1f4731bba
Author: Steven Varoumas <steven.varoumas at huawei.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/IndexOps.td
A mlir/python/mlir/dialects/index.py
A mlir/test/python/dialects/index_dialect.py
Log Message:
-----------
[mlir][python] Enable python bindings for Index dialect (#85827)
This small patch enables python bindings for the index dialect.
---------
Co-authored-by: Steven Varoumas <steven.varoumas1 at huawei.com>
Commit: 75dfa58ea93aa93b97534906778cb3dd24ba841a
https://github.com/llvm/llvm-project/commit/75dfa58ea93aa93b97534906778cb3dd24ba841a
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/docs/RemoveDIsDebugInfo.md
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/Instruction.h
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
Log Message:
-----------
[RemoveDIs][NFC] Rename DPMarker->DbgMarker (#85931)
Another trivial rename patch, the last big one for now, which renamed
DPMarkers to DbgMarkers. This required the field `DbgMarker` in
`Instruction` to be renamed to `DebugMarker` to avoid a clash, but
otherwise was a simple string substitution of `s/DPMarker/DbgMarker` and
a manual renaming of `DPM` to `DM` in the few places where that acronym
was used for debug markers.
Commit: 407937036fa7640f61f225474b1ea6623a40dbdd
https://github.com/llvm/llvm-project/commit/407937036fa7640f61f225474b1ea6623a40dbdd
Author: Martin Storsjö <martin at martin.st>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M libcxx/modules/CMakeLists.txt
Log Message:
-----------
Revert "[libcxx] [modules] Fix relative paths with absolute LIBCXX_INSTALL_MODULES_DIR (#85756)"
This reverts commit 272d1b44efdedb68c194970a610f0ca1b7b769c5,
and the follow-up fix in d209d1340b99d4fbd325dffb5e13b757ab8264ea.
Even after the follow-up fix, building with an empty
CMAKE_INSTALL_PREFIX errors out with errors like this:
CMake Error at /b/s/w/ir/x/w/llvm-llvm-project/libcxx/modules/CMakeLists.txt:215 (file):
file RELATIVE_PATH must be passed a full path to the directory:
lib/x86_64-pc-windows-msvc
Commit: 12028cb1dab9ba1b4ac826c3d70ca19c3b379255
https://github.com/llvm/llvm-project/commit/12028cb1dab9ba1b4ac826c3d70ca19c3b379255
Author: Will Hawkins <hawkinsw at obs.cr>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
Log Message:
-----------
[DwarfGenerator] Calculate relative offset according to Dwarf Version (#84847)
The relative offset for a CU in Dwarf v5 (and later) is different than
the relative offset for a CU in Dwarf v4 (and before).
Signed-off-by: Will Hawkins <hawkinsw at obs.cr>
Commit: 1b5b4eebb6a012cf223954013d34c6e896720822
https://github.com/llvm/llvm-project/commit/1b5b4eebb6a012cf223954013d34c6e896720822
Author: Thurston Dang <thurston at google.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M compiler-rt/lib/memprof/memprof_allocator.h
Log Message:
-----------
[memprof] Move allocator base to avoid conflict with high-entropy ASLR (#85834)
memprof often fails when ASLR entropy is too high ('sudo sysctl
vm.mmap_rnd_bits=32; ninja check-memprof'), which is the default setting
for newer versions of Ubuntu
(https://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/jammy/commit/?h=hwe-6.5-next--2024.03.04-1--auto&id=6b522637c6a7dabd8530026ae933fb5ff17e877f).
This patch fixes the issue by moving the allocator base, analogously to
ASan (https://reviews.llvm.org/D148280).
Explanation from the ASan patch: when CONFIG_ARCH_MMAP_RND_BITS == 32,
it will frequently conflict with memprof's allocator, because the PIE
program segment base address of 0x555555555554 plus an ASLR shift of up
to ((2**32) * 4K == 0x100000000000) will sometimes exceed memprof's
hardcoded base address of 0x600000000000. We fix this by simply moving
the allocator base to 0x500000000000, which is below the PIE program
segment base address. This is cleaner than trying to move it to another
location that is sandwiched between the PIE program and library
segments, because if either of those grow too large, it will collide
with the allocator region.
Note that we will never need to change this base address again (unless
we want to increase the size of the allocator), because ASLR cannot be
set above 32-bits for x86-64 Linux (the PIE program segment and library
segments would collide with each other; see also ARCH_MMAP_RND_BITS_MAX
in https://github.com/torvalds/linux/blob/master/arch/x86/Kconfig).
Commit: a6a6066290679f23f2bd6b27afc7a06aab07590f
https://github.com/llvm/llvm-project/commit/a6a6066290679f23f2bd6b27afc7a06aab07590f
Author: Eric Li <li.zhe.hua at gmail.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/AdornedCFG.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Fix crash when analyzing a coroutine (#85957)
A coroutine function body (`CoroutineBodyStmt`) may have null children,
which causes `isa` to segfault.
Commit: 9cb5004209323d6fa8af8c41e456818c20585984
https://github.com/llvm/llvm-project/commit/9cb5004209323d6fa8af8c41e456818c20585984
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-version.cpp
Log Message:
-----------
Reland [FMV] Emit the resolver along with the default version definit… (#85923)
…ion.
This was reverted because the resolver didn't look as expected in one of
the tests. I believe it had some interaction with #84146. I have now
regenerated it using -target-feature -fp-armv8.
Commit: 0e47dfede468a292dd8cd893d6d0179052501383
https://github.com/llvm/llvm-project/commit/0e47dfede468a292dd8cd893d6d0179052501383
Author: Fangrui Song <i at maskray.me>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Add isStaticRelSecType to simplify SHT_REL/SHT_RELA testing. NFC
and make it easier to introduce a new relocation format.
https://discourse.llvm.org/t/rfc-relleb-a-compact-relocation-format-for-elf/77600
Pull Request: https://github.com/llvm/llvm-project/pull/85893
Commit: 25d61be8a5e563988661709c5d01f67c06b388e2
https://github.com/llvm/llvm-project/commit/25d61be8a5e563988661709c5d01f67c06b388e2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M clang/test/CodeGen/X86/avx-shuffle-builtins.c
Log Message:
-----------
[X86] avx-shuffle-builtins.c - limit to x86 targets
Attempt to fix issue with non-x86 buildbots (sorry its blind but I can't test this)
Commit: decd88ef0538504707c5d1f0fd8b9de60a5b9b4c
https://github.com/llvm/llvm-project/commit/decd88ef0538504707c5d1f0fd8b9de60a5b9b4c
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M llvm/include/llvm/IR/DebugProgramInstruction.h
Log Message:
-----------
[RemoveDIs][NFC] Delete a now-redundant comment
Submitted without review for being a trivial comment-only change, deletes
a line that requests the DbgLabelRecord class be renamed to DbgLabelRecord
in the future.
Commit: b754e6f6900e8c4205567fb2a13ff3c90811f5bc
https://github.com/llvm/llvm-project/commit/b754e6f6900e8c4205567fb2a13ff3c90811f5bc
Author: Job Henandez Lara <jobhdezlara93 at gmail.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M libc/test/src/math/smoke/FMaxTest.h
Log Message:
-----------
Fix typo (#85869)
Commit: b20360abeb3a80281dc082f1e093abd13cb1ee4c
https://github.com/llvm/llvm-project/commit/b20360abeb3a80281dc082f1e093abd13cb1ee4c
Author: AdityaK <hiraditya at msn.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/Driver/riscv-features.c
Log Message:
-----------
clang driver: enable fast unaligned access for Android on RISCV64 (#85704)
Android CTS test already requires fast unaligned access
https://android-review.googlesource.com/c/platform/cts/+/2675633
Commit: 783569c7a0f71d2964189e398473d79f5c6bbd19
https://github.com/llvm/llvm-project/commit/783569c7a0f71d2964189e398473d79f5c6bbd19
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-03-20 (Wed, 20 Mar 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/AdornedCFG.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/CodeGen/X86/avx-shuffle-builtins.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/Driver/riscv-features.c
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M compiler-rt/lib/memprof/memprof_allocator.h
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/default-clause-byref.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction-rename.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction-byref.f90
M flang/test/Lower/OpenMP/parallel-wsloop-reduction.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-2-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul.f90
M libc/test/src/math/smoke/FMaxTest.h
M libc/utils/gpu/loader/amdgpu/Loader.cpp
M libcxx/modules/CMakeLists.txt
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Writer.cpp
M llvm/docs/RemoveDIsDebugInfo.md
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/Instruction.h
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-fcmp.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-isnan.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/pr64645.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
M llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/SystemZ/int-cmp-56.mir
M llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
A llvm/test/CodeGen/WebAssembly/pr63817.ll
M llvm/test/CodeGen/X86/callbr-asm-kill.mir
M llvm/test/CodeGen/X86/regalloc-copy-hints.mir
M llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
M llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
M llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
M llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
R llvm/test/MachineVerifier/test_adjustsstack.mir
M llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/IndexOps.td
A mlir/python/mlir/dialects/index.py
A mlir/test/python/dialects/index_dialect.py
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
Rebase, fix formatting
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/cafdc5a1153e...783569c7a0f7
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