[all-commits] [llvm/llvm-project] 30ab58: [MLIR][LLVM][SROA] Support incorrectly typed memor...

[Christian Ulmann via All-commits]

  Branch: refs/heads/users/dinistro/mlir-llvm-sroa-remove-type-consistency
  Home:   https://github.com/llvm/llvm-project
  Commit: 30ab58297047bfe7737946fa2eff16f224dd8c4e
      https://github.com/llvm/llvm-project/commit/30ab58297047bfe7737946fa2eff16f224dd8c4e
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2024-03-20 (Wed, 20 Mar 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/LLVMIR/Transforms/TypeConsistency.h
    M mlir/include/mlir/Interfaces/MemorySlotInterfaces.h
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
    M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/sroa.mlir
    M mlir/test/Dialect/LLVMIR/type-consistency.mlir

  Log Message:
  -----------
  [MLIR][LLVM][SROA] Support incorrectly typed memory accesses

This commit relaxes the assumption of type consistency for LLVM dialect
load and store operations in SROA. Instead, there is now a check that
loads and stores are in the bounds specified by the sub-slot they
access.

This commit additionally removes the corresponding patterns from the
type consistency pass, as they are no longer necessary.


  Commit: 1d720cd60330688111a22ac3dea253c25151e189
      https://github.com/llvm/llvm-project/commit/1d720cd60330688111a22ac3dea253c25151e189
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2024-03-20 (Wed, 20 Mar 2024)

  Changed paths:
    M mlir/include/mlir/Interfaces/MemorySlotInterfaces.h
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/sroa.mlir

  Log Message:
  -----------
  address review comments


Compare: https://github.com/llvm/llvm-project/compare/9751e1a38508...1d720cd60330

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