[all-commits] [llvm/llvm-project] 42f511: [RISCV] Add test case for miscompile in gather -> ...

[Luke Lau via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 42f511c95c6f58a2ed8d6fe35af1cde14c750342
      https://github.com/llvm/llvm-project/commit/42f511c95c6f58a2ed8d6fe35af1cde14c750342
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-19 (Tue, 19 Mar 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  -----------
  [RISCV] Add test case for miscompile in gather -> strided load combine. NFC

This shows the issue in #82430, but triggers it via the widening SEW combine
rather than a GEP that RISCVGatherScatterLowering doesn't detect.

(cherry picked from commit 2cd59bdc891ab59a1abfe5205feb45791a530a47)


  Commit: a9d4ed71707d36bc554bfe38408c74c285b11e6b
      https://github.com/llvm/llvm-project/commit/a9d4ed71707d36bc554bfe38408c74c285b11e6b
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-19 (Tue, 19 Mar 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  -----------
  [RISCV] Adjust test case to show wrong stride. NFC

See https://github.com/llvm/llvm-project/pull/82506#discussion_r1498080785

(cherry picked from commit 11d115d0569b212dfeb7fe6485be48070e068e19)


  Commit: a2c93b34dfdf6b2e5d16a5068e92f30bbc5d0ba7
      https://github.com/llvm/llvm-project/commit/a2c93b34dfdf6b2e5d16a5068e92f30bbc5d0ba7
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-19 (Tue, 19 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  -----------
  [RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (#82506)

This fixes the miscompile reported in #82430 by telling
isSimpleVIDSequence to sign extend to XLen instead of the width of the
indices, since the "sequence" of indices generated by a strided load
will be at XLen.

This was the simplest way I could think of getting isSimpleVIDSequence
to treat the indexes as if they were zero extended to XLenVT.

Another way we could do this is by refactoring out the "get constant
integers" part from isSimpleVIDSequence and handle them as APInts so we
can separately zero extend it.

Fixes #82430

(cherry picked from commit 815644b4dd882ade2e5649d4f97c3dd6f7aea200)


Compare: https://github.com/llvm/llvm-project/compare/53ea0de61dcd...a2c93b34dfdf

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