[all-commits] [llvm/llvm-project] c48d81: [RISCV] Add SiFiveP600Model SchedModel that is use...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c48d8182f172ac24244d5fb038b7ab983f67def4
      https://github.com/llvm/llvm-project/commit/c48d8182f172ac24244d5fb038b7ab983f67def4
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-03-18 (Mon, 18 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

  Log Message:
  -----------
  [RISCV] Add SiFiveP600Model SchedModel that is used by sifive-p670 (#84962)

This PR includes an initial scheduler model shows improvement on
multiple workloads over NoSchedModel and SiFive7Model for sifive-p670.
We plan on making significant changes to this model in the future so
that it is more accurate. This patch would close
https://github.com/llvm/llvm-project/pull/80612.



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