[all-commits] [llvm/llvm-project] 295cdd: [ARM][TableGen][MC] Change the ARM mnemonic operan...

[Alfie Richards via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 295cdd5c3dbd14406bf9cce01e3dfd787fb1ddda
      https://github.com/llvm/llvm-project/commit/295cdd5c3dbd14406bf9cce01e3dfd787fb1ddda
  Author: Alfie Richards <156316945+AlfieRichardsArm at users.noreply.github.com>
  Date:   2024-03-18 (Mon, 18 Mar 2024)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/ARM/ARM.td
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrThumb.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/test/MC/ARM/arm-branch-errors.s
    M llvm/test/MC/ARM/arm11-hint-instr.s
    M llvm/test/MC/ARM/cde-fp-vec.s
    M llvm/test/MC/ARM/cde-vec-pred.s
    M llvm/test/MC/ARM/cps.s
    M llvm/test/MC/ARM/diagnostics.s
    M llvm/test/MC/ARM/directive-arch_extension-crypto.s
    M llvm/test/MC/ARM/invalid-fp-armv8.s
    M llvm/test/MC/ARM/lsl-zero-errors.s
    M llvm/test/MC/ARM/mve-load-store.s
    M llvm/test/MC/ARM/mve-misc.s
    M llvm/test/MC/ARM/neon-complex.s
    M llvm/test/MC/ARM/no-mve.s
    M llvm/test/MC/ARM/not-armv4.s
    M llvm/test/MC/ARM/register-token-source-loc.s
    M llvm/test/MC/ARM/tMOVSr.s
    M llvm/test/MC/ARM/thumb-diagnostics.s
    M llvm/test/MC/ARM/thumb-mov.s
    M llvm/test/MC/ARM/thumb2-diagnostics.s
    M llvm/test/MC/ARM/vfp4.s
    M llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (#83436)

This changs the way the assembly matcher works for Aarch32 parsing.
Previously there was a pile of hacks which dictated whether the CC,
CCOut, and VCC operands should be present which de-facto chose if the
wide/narrow (or thumb1/thumb2/arm) instruction version were chosen.

This meant much of the TableGen machinery present for the assembly
matching was effectively being bypassed and worked around.

This patch makes the CC and CCOut operands optional which allows the ASM
matcher operate as it was designed and means we can avoid doing some of
the hacks done previously. This also adds the option for the target to
allow the prioritizing the smaller instruction encodings as is required
for Aarch32.



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