[all-commits] [llvm/llvm-project] 620544: [RISCV] Add sched classes for Zbb integer min max ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 620544192477cb8f4f1a1342e9593f7f15b5ecaf
      https://github.com/llvm/llvm-project/commit/620544192477cb8f4f1a1342e9593f7f15b5ecaf
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-03-14 (Thu, 14 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    M llvm/lib/Target/RISCV/RISCVScheduleZb.td

  Log Message:
  -----------
  [RISCV] Add sched classes for Zbb integer min max instructions


  Commit: 818e0272f5142986e8d82d1267fb6aa21cd168a0
      https://github.com/llvm/llvm-project/commit/818e0272f5142986e8d82d1267fb6aa21cd168a0
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-03-14 (Thu, 14 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s

  Log Message:
  -----------
  [RISCV] Model integer min max instructions from Zbb execute in late-B ALU

We don't model the early vs late ALU so we just need to remove usage of
SiFivePipeA for these instructions.


Compare: https://github.com/llvm/llvm-project/compare/b97c12936dd8...818e0272f514

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