[all-commits] [llvm/llvm-project] 65f5e2: [RISC-V] Add another missing cast in .td file (#85...

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65f5e2c4070f22ab7a1617c798b4c61baa9b39a8
      https://github.com/llvm/llvm-project/commit/65f5e2c4070f22ab7a1617c798b4c61baa9b39a8
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2024-03-14 (Thu, 14 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISC-V] Add another missing cast in .td file (#85055)

Another instance where we produce an instruction that defines a vreg
with an i32 value.



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