[all-commits] [llvm/llvm-project] 65f07b: [MIPS] Introduce NAL instruction support for Mipsr...

[anbbna via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65f07b804c2c05cf49bd043f2a6e9a0020198165
      https://github.com/llvm/llvm-project/commit/65f07b804c2c05cf49bd043f2a6e9a0020198165
  Author: anbbna <117081688+anbbna at users.noreply.github.com>
  Date:   2024-03-13 (Wed, 13 Mar 2024)

  Changed paths:
    M llvm/lib/Target/Mips/Mips32r6InstrFormats.td
    M llvm/lib/Target/Mips/Mips32r6InstrInfo.td
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/lib/Target/Mips/MipsScheduleGeneric.td
    A llvm/test/MC/Mips/mips32/nal.s
    A llvm/test/MC/Mips/mips32r6/nal.s

  Log Message:
  -----------
  [MIPS] Introduce NAL instruction support for Mipsr6 and prer6 (#84429)

NAL is an assembly idiom on Pre-R6 instruction sets (which is
implemented in binutils), or an actual instruction on Release 6
instruction set, and is used to read the PC, due to the nature of the
MIPS architecture.

Since we can't read the PC directly, on pre-R6 we use a always-not-taken
Branch and Link operation to the address of the next instruction, which
effectively writes the address to $31, thus PC is read with offset +8.

MIPS Release 6 removed the conventional Branch and Link instructions,
but kept NAL as an actual instruction for compatibility on the assembly
level. The instruction has the same encoding of the pre-R6 ones, and
with the same behavior: PC + 8 -> $31.



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