[all-commits] [llvm/llvm-project] 1d900e: [AArch64][GlobalISel] Avoid generating inserts for...

[Dhruv Chawla (work) via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d900e298449d43547312364751f730b7a0d07d1
      https://github.com/llvm/llvm-project/commit/1d900e298449d43547312364751f730b7a0d07d1
  Author: Dhruv Chawla (work) <dhruvc at nvidia.com>
  Date:   2024-03-12 (Tue, 12 Mar 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
    M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/abs.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/bitcast.ll
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/fabs.ll
    M llvm/test/CodeGen/AArch64/faddsub.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fcvt.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fexplog.ll
    M llvm/test/CodeGen/AArch64/fminimummaximum.ll
    M llvm/test/CodeGen/AArch64/fminmax.ll
    M llvm/test/CodeGen/AArch64/fmla.ll
    M llvm/test/CodeGen/AArch64/fmul.ll
    M llvm/test/CodeGen/AArch64/fneg.ll
    M llvm/test/CodeGen/AArch64/fpext.ll
    M llvm/test/CodeGen/AArch64/fpow.ll
    M llvm/test/CodeGen/AArch64/fpowi.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fptrunc.ll
    M llvm/test/CodeGen/AArch64/frem.ll
    M llvm/test/CodeGen/AArch64/fsincos.ll
    M llvm/test/CodeGen/AArch64/fsqrt.ll
    M llvm/test/CodeGen/AArch64/icmp.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/llvm.exp10.ll
    M llvm/test/CodeGen/AArch64/load.ll
    M llvm/test/CodeGen/AArch64/sext.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/xtn.ll
    M llvm/test/CodeGen/AArch64/zext.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Avoid generating inserts for undefs when selecting G_BUILD_VECTOR (#84452)

It is safe to ignore undef values when selecting G_BUILD_VECTOR as undef
values choose random registers for copying values from.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications