[all-commits] [llvm/llvm-project] d8d2de: [RISCV] Handle FP riscv_masked_strided_load with 0...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d8d2dea7fc6f452ac6a24948fe3ff99920f81c99
      https://github.com/llvm/llvm-project/commit/d8d2dea7fc6f452ac6a24948fe3ff99920f81c99
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-10 (Sun, 10 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll

  Log Message:
  -----------
  [RISCV] Handle FP riscv_masked_strided_load with 0 stride. (#84576)

Previously, we tried to create an integer extending load. We need to a
non-extending FP load instead.

Fixes #84541.



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