[all-commits] [llvm/llvm-project] 5f935e: [AArch64] Optimize fp64 <-> fp16 SIMD conversions

[David Majnemer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f935e91810eb28854611faf13bb7d07a8dbf470
      https://github.com/llvm/llvm-project/commit/5f935e91810eb28854611faf13bb7d07a8dbf470
  Author: David Majnemer <david.majnemer at gmail.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
    M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/fpext.ll
    M llvm/test/CodeGen/AArch64/fptrunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/vector-fcopysign.ll

  Log Message:
  -----------
  [AArch64] Optimize fp64 <-> fp16 SIMD conversions

Legalization would result in needless scalarization. Add some
DAGCombines to fix this up.


  Commit: edc1c3d24e6f8ed548340ce0369138fb40427a24
      https://github.com/llvm/llvm-project/commit/edc1c3d24e6f8ed548340ce0369138fb40427a24
  Author: David Majnemer <david.majnemer at gmail.com>
  Date:   2024-03-08 (Fri, 08 Mar 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/faddp-half.ll
    M llvm/test/CodeGen/AArch64/faddsub.ll
    M llvm/test/CodeGen/AArch64/fcvt.ll
    M llvm/test/CodeGen/AArch64/fcvt_combine.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fmla.ll
    M llvm/test/CodeGen/AArch64/fmul.ll
    M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll

  Log Message:
  -----------
  [AArch64] Make more vector f16 operations legal

v8f16 is a legal type but promoting to v16f16 would result in an illegal
type.

Let's legalize these by a combination of splitting+promoting resulting
in a pair of v4f16.

Also, we were being overly cautious with different v4f16 nodes. Mark
more of them safe to promote to v4f32.


Compare: https://github.com/llvm/llvm-project/compare/e963d0740e64...edc1c3d24e6f

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