[all-commits] [llvm/llvm-project] ecf7db: [lldb] Disable shell tests affected by ld_new bug ...
Florian Mayer via All-commits
all-commits at lists.llvm.org
Thu Mar 7 16:02:56 PST 2024
Branch: refs/heads/users/fmayer/spr/main.nfc-hwasan-factor-getpcfp-out-of-hwasan-class
Home: https://github.com/llvm/llvm-project
Commit: ecf7db8b52d7061ef8f14c1f7b6fcc370072d087
https://github.com/llvm/llvm-project/commit/ecf7db8b52d7061ef8f14c1f7b6fcc370072d087
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M lldb/test/Shell/Unwind/eh-frame-dwarf-unwind.test
M lldb/test/Shell/Unwind/thread-step-out-ret-addr-check.test
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] Disable shell tests affected by ld_new bug (#84246)
Equivalent to the changes made in https://github.com/llvm/llvm-project/pull/83941,
except to support shell tests.
Commit: 641b98a0d1e20da9500aa012ced41e53967a423f
https://github.com/llvm/llvm-project/commit/641b98a0d1e20da9500aa012ced41e53967a423f
Author: Amara Emerson <amara at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
Log Message:
-----------
[GlobalISel] Fix crash in tryFoldAndOrOrICmpsUsingRanges() with pointer types.
Commit: 143afb405a7e12e3fe1622b92f046ab2380c8981
https://github.com/llvm/llvm-project/commit/143afb405a7e12e3fe1622b92f046ab2380c8981
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
A bolt/test/X86/linux-alt-instruction.s
Log Message:
-----------
[BOLT] Add reading support for Linux kernel .altinstructions section (#84283)
Read .altinstructions and annotate instructions that have alternative
sequences with "AltInst" annotation. Note that some instructions may
have more than one alternatives, in which case they will have multiple
annotations in the form "AltInst", "AltInst2", "AltInst3", etc.
Commit: 9cf9cb271bf86bda4996be9a31fa413381f2f5e3
https://github.com/llvm/llvm-project/commit/9cf9cb271bf86bda4996be9a31fa413381f2f5e3
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseExpr.cpp
A clang/test/CodeGen/attr-availability-visionos.c
A clang/test/Sema/attr-availability-visionos.c
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
Log Message:
-----------
[clang] Upstream visionOS Availability & DarwinSDKInfo APIs (#84279)
Admittedly a bit awkward, `visionos` is the correct and accepted
spelling for annotating availability for xrOS target triples. This patch
detects errors and handles cases when `xros` is mistakenly passed.
In addition, add APIs for introduced/deprecated/obsoleted versioning in
DarwinSDKInfo mappings.
Commit: ced1fac8a32e35b63733bda27c7f5b9a2b635403
https://github.com/llvm/llvm-project/commit/ced1fac8a32e35b63733bda27c7f5b9a2b635403
Author: Yinying Li <yinyingli at google.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Log Message:
-----------
[mlir][sparse] Move n:m printing into toMLIRString (#84264)
Commit: 167b90d0401d0fe488195c7e3d6fc1edc8fc5d94
https://github.com/llvm/llvm-project/commit/167b90d0401d0fe488195c7e3d6fc1edc8fc5d94
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
A clang/test/CodeGen/tbaa-struct-relaxed-aliasing-with-tsan.cpp
Log Message:
-----------
[TBAA] Add test showing tbaa.struct being generated with relaxed-alias.
Add test showing that tbaa.struct is generated when using TSan with
relaxed-aliasing.
Commit: a0c7714525b696d90d2021249f9105c24ca7adcc
https://github.com/llvm/llvm-project/commit/a0c7714525b696d90d2021249f9105c24ca7adcc
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
Log Message:
-----------
[RISCV] Split div vs rem scheduling information [nfc] (#84385)
Allows a processor to define different latencies for the two operations.
Commit: f78129e2bbafdd04a71bc09fc44e0797dd08db05
https://github.com/llvm/llvm-project/commit/f78129e2bbafdd04a71bc09fc44e0797dd08db05
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
Log Message:
-----------
[Orc] Add NotifyCreated callback for LLJITBuilder (#84175)
This is useful to attach generators to JITDylibs or inject initial
symbol definitions.
Commit: 2a4a852a67eab2f8d0533c23719b1bd08d6edea9
https://github.com/llvm/llvm-project/commit/2a4a852a67eab2f8d0533c23719b1bd08d6edea9
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Interpreter/CMakeLists.txt
A clang/unittests/Interpreter/IncrementalCompilerBuilderTest.cpp
Log Message:
-----------
Reland [clang-repl] Expose setter for triple in IncrementalCompilerBuilder (#84174)
With out-of-process execution the target triple can be different from
the one on the host. We need an interface to configure it.
Relanding this with cleanup-fixes in the unittest.
Commit: 23d2c388303982e4341f248120915328a6444b51
https://github.com/llvm/llvm-project/commit/23d2c388303982e4341f248120915328a6444b51
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
Log Message:
-----------
[gn build] Port 2a4a852a67ea
Commit: 49b1fc4f831a047bd6ffde9ba19612c329dc5166
https://github.com/llvm/llvm-project/commit/49b1fc4f831a047bd6ffde9ba19612c329dc5166
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/urem-expansion.ll
Log Message:
-----------
[CVP] Freeze Y when expanding urem x, y with X < 2Y (#84390)
We're going from a single use to two independent uses, we need these two
to see consistent values for undef. As an example, consider x = 0x2 when
y = 0b00u1. If the sub use picks 0b0001 and the cmp use picks 0b0011,
that would be incorrect.
Commit: 48673825f47cbac9cd7c61299ca8d01579314ae0
https://github.com/llvm/llvm-project/commit/48673825f47cbac9cd7c61299ca8d01579314ae0
Author: Lang Hames <lhames at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Deallocate FinalizedAllocs on error paths in notifyEmitted.
If notifyEmitted encounters a failure (either because some plugin returned one,
or because the ResourceTracker was defunct) then we need to deallocate the
FinalizedAlloc manually.
No testcase yet: This requires a concurrent setup -- we'll need to build some
infrastructure to coordinate links and deliberately injected failures in order
to reliably test this.
Commit: 69b8bc71110aca64c74a14800e800f4b151d5d6f
https://github.com/llvm/llvm-project/commit/69b8bc71110aca64c74a14800e800f4b151d5d6f
Author: dyung <douglas.yung at sony.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M cross-project-tests/debuginfo-tests/llgdb-tests/static-member-2.cpp
M cross-project-tests/debuginfo-tests/llgdb-tests/static-member.cpp
Log Message:
-----------
[Dexter] Extend XFAIL of Dexter tests to all MacOS architectures. (#83936)
I am trying to bring up a MacOS buildbot targeting x86 and noticed that
two Dexter tests were failing,
cross-project-tests/debuginfo-tests/llgdb-tests/static-member.cpp and
cross-project-tests/debuginfo-tests/llgdb-tests/static-member-2.cpp.
Looking in the history for these tests, they were XFAILed for Apple
Silicon in 9c46606 and are failing similar on x86 for me, so we should extend
the XFAIL to all MacOS architectures.
Commit: 3a56b5a27d711aaa141c354706638bd94f7460a3
https://github.com/llvm/llvm-project/commit/3a56b5a27d711aaa141c354706638bd94f7460a3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/test/Driver/cuda-phases.cu
Log Message:
-----------
[CUDA] Include PTX in non-RDC mode using the new driver (#84367)
Summary:
The old driver embed PTX in rdc-mode and so does the `nvcc` compiler.
The new drivers currently does not do this, so we should keep it
consistent in this case. This simply requires adding the assembler
output as an input to the offloading action that gets fed to fatbin.
Commit: 14171b87a3b5a403f39d78da964595175636a0ae
https://github.com/llvm/llvm-project/commit/14171b87a3b5a403f39d78da964595175636a0ae
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/stdfix.rst
M libc/spec/llvm_libc_stdfix_ext.td
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/exphk.cpp
A libc/src/stdfix/exphk.h
A libc/src/stdfix/expk.cpp
A libc/src/stdfix/expk.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/ExpTest.h
A libc/test/src/stdfix/exphk_test.cpp
A libc/test/src/stdfix/expk_test.cpp
Log Message:
-----------
[libc][stdfix] Add exp function for short _Accum and _Accum types. (#84391)
Commit: 909ab0e0d1903ad2329ca9fdf248d21330f9437f
https://github.com/llvm/llvm-project/commit/909ab0e0d1903ad2329ca9fdf248d21330f9437f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/iabs.ll
A llvm/test/CodeGen/RISCV/pr84200.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
Log Message:
-----------
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
Select blocks poison, but AND/OR do not. We need to insert a freeze
to block poison propagation.
This creates suboptimal codegen which I will try to fix with other
patches. I'm prioritizing the correctness fix since we have 2 bug reports.
Fixes #84200 and #84350
Commit: d93a126090b6e772d3b96f201cdd44ea0d6360ef
https://github.com/llvm/llvm-project/commit/d93a126090b6e772d3b96f201cdd44ea0d6360ef
Author: Alex Langford <alangford at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/test/API/lang/c/tls_globals/TestTlsGlobals.py
Log Message:
-----------
[lldb] Add ability to detect darwin host linker version to xfail tests (#83941)
When Apple released its new linker, it had a subtle bug that caused
LLDB's TLS tests to fail. Unfortunately this means that TLS tests are
not going to work on machines that have affected versions of the linker,
so we should annotate the tests so that they only work when we are
confident the linker has the required fix.
I'm not completely satisfied with this implementation. That being said,
I believe that adding suport for linker versions in general is a
non-trivial change that would require far more thought. There are a few
challenges involved:
- LLDB's testing infra takes an argument to change the compiler, but
there's no way to switch out the linker.
- There's no standard way to ask a compiler what linker it will use.
- There's no standard way to ask a linker what its version is. Many
platforms have the same name for their linker (ld).
- Some platforms automatically switch out the linker underneath you. We
do this for Windows tests (where we use LLD no matter what).
Given that this is affecting the tests on our CI, I think this is an
acceptable solution in the interim.
Commit: 1c01651bda46426f497c2948fe52cc25acf0e76d
https://github.com/llvm/llvm-project/commit/1c01651bda46426f497c2948fe52cc25acf0e76d
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M libc/docs/index.rst
A libc/docs/talks.rst
Log Message:
-----------
[libc][docs] add page linking to talks (#84393)
Commit: 10edabbcf331fdd53d27c5195de1b692a0063721
https://github.com/llvm/llvm-project/commit/10edabbcf331fdd53d27c5195de1b692a0063721
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
A llvm/test/CodeGen/X86/GlobalISel/legalize-sdiv.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-srem.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-udiv.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
A llvm/test/CodeGen/X86/isel-sdiv.ll
A llvm/test/CodeGen/X86/isel-srem.ll
A llvm/test/CodeGen/X86/isel-udiv.ll
A llvm/test/CodeGen/X86/isel-urem.ll
Log Message:
-----------
[X86][GlobalISel] Enable G_SDIV/G_UDIV/G_SREM/G_UREM (#81615)
* Create a libcall for s64 type for 32 bit targets.
* Fix a bug in REM selection: SUBREG_TO_REG is not intended to produce a
value from super registers.
* Replace selector tests by end-to-end tests. Other passes
check the selected MIR better.
Commit: 5d33f7176b002da244823ca0e6b524777890dd9d
https://github.com/llvm/llvm-project/commit/5d33f7176b002da244823ca0e6b524777890dd9d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
Log Message:
-----------
Fix build: llvm::Error needs to be moved for implicit conversion to Expected.
I don't know why the premerge setup didn't fail on this, but many
builbots are broken right now.
Commit: 5669660f37ef1800f4a7852577364b024d75e3d8
https://github.com/llvm/llvm-project/commit/5669660f37ef1800f4a7852577364b024d75e3d8
Author: Chao Chen <116223022+chencha3 at users.noreply.github.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/CMakeLists.txt
A mlir/include/mlir/Dialect/XeGPU/CMakeLists.txt
A mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/InitAllDialects.h
M mlir/lib/Dialect/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
A mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
Log Message:
-----------
[MLIR] XeGPU dialect for Intel GPU - core definitions and base classes (#78483)
This PR follows our previous [RFC
](https://discourse.llvm.org/t/rfc-add-xegpu-dialect-for-intel-gpus/75723)
to add XeGPU dialect definition for Intel GPUs. It contains dialect,
type, attributes and operators definitions, as well as testcases for
semantic checks. The lowering and optimization passes will be issued
with separated passes.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: a9b0d7590b9e08151243b97aa75366e988e0d6c8
https://github.com/llvm/llvm-project/commit/a9b0d7590b9e08151243b97aa75366e988e0d6c8
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
M bolt/test/X86/linux-alt-instruction.s
Log Message:
-----------
[BOLT] Properly propagate Cursor errors (#84378)
Handle out-of-bounds reading errors correctly in LinuxKernelRewriter.
Commit: 50ae8a2a38b618d76193bed04b1d7df6890d5c8a
https://github.com/llvm/llvm-project/commit/50ae8a2a38b618d76193bed04b1d7df6890d5c8a
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M clang/include/clang/InstallAPI/Frontend.h
M clang/include/clang/InstallAPI/Visitor.h
M clang/lib/InstallAPI/Frontend.cpp
M clang/lib/InstallAPI/Visitor.cpp
A clang/test/InstallAPI/functions.test
M clang/tools/clang-installapi/Options.cpp
M llvm/include/llvm/TextAPI/Record.h
M llvm/include/llvm/TextAPI/RecordsSlice.h
M llvm/lib/TextAPI/RecordsSlice.cpp
M llvm/unittests/TextAPI/RecordTests.cpp
Log Message:
-----------
[InstallAPI] Collect global functions (#83952)
* Include whether functions are inlinable as they impact whether to add
them into the tbd file and for future verification.
* Fix how clang arguments got passed along, previously spacing was
passed along to CC1 causing search path inputs to look non-existent.
Commit: 3712edbdbb79e0169acf0c57e111f3195006c013
https://github.com/llvm/llvm-project/commit/3712edbdbb79e0169acf0c57e111f3195006c013
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M libc/docs/c23.rst
Log Message:
-----------
[libc] finish documenting c23 additions (#84383)
- [libc] finish documenting c23 additions
- sort according to appearance in Annex B and section 7
Commit: 293ec4865bfcb6df2091ef4bcce706a566794b5c
https://github.com/llvm/llvm-project/commit/293ec4865bfcb6df2091ef4bcce706a566794b5c
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M libc/src/__support/CPP/bit.h
M libc/src/__support/UInt.h
M libc/src/stdbit/stdc_count_ones_uc.cpp
M libc/src/stdbit/stdc_count_ones_ui.cpp
M libc/src/stdbit/stdc_count_ones_ul.cpp
M libc/src/stdbit/stdc_count_ones_ull.cpp
M libc/src/stdbit/stdc_count_ones_us.cpp
M libc/test/src/__support/CPP/bit_test.cpp
Log Message:
-----------
[libc] rename cpp::count_ones to cpp::popcount to better mirror std:: (#84388)
libc/src/__support/CPP/bit.h and cpp:: is meant to mirror std::. Fix the
TODO.
Commit: f862265733d65efbfd819408b594b3b2854491d2
https://github.com/llvm/llvm-project/commit/f862265733d65efbfd819408b594b3b2854491d2
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
Log Message:
-----------
AMDGPU: Use True16Predicate for UseRealTrue16Insts in VOP2 Reals (#84394)
We can not use OtherPredicates or SubtargetPredicate because they
should be copied from pseudo to real, and we should not override them.
Commit: a01e9ce86f4c1bc9af819902db9f287b6d23f54f
https://github.com/llvm/llvm-project/commit/a01e9ce86f4c1bc9af819902db9f287b6d23f54f
Author: Amara Emerson <amara at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
Log Message:
-----------
[AArc64][GlobalISel] Fix legalizer assert for G_INSERT_VECTOR_ELT
We should moreElements <3 x s1> to <4 x s1> before we try to widen the element,
otherwise we end up with a <3 x s21> nonsense type.
Commit: 3e5afba8ef9319956d288ff755df3c442433eb88
https://github.com/llvm/llvm-project/commit/3e5afba8ef9319956d288ff755df3c442433eb88
Author: Florian Mayer <fmayer at google.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC] [hwasan] be consistent about how to get integer types (#84396)
Commit: ddf79deb42d901fbb732e56464efbf93bc444070
https://github.com/llvm/llvm-project/commit/ddf79deb42d901fbb732e56464efbf93bc444070
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
Log Message:
-----------
[Asan] Fix -Wunused-private-field in non-assertion builds (NFC)
llvm-project/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp:650:13:
error: private field 'OwnerFn' is not used [-Werror,-Wunused-private-field]
Function *OwnerFn = nullptr;
^
1 error generated.
Commit: 8bf8d36f8e82a1e2d32f33dbe7369d9cecd57f46
https://github.com/llvm/llvm-project/commit/8bf8d36f8e82a1e2d32f33dbe7369d9cecd57f46
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
[compiler-rt][fuzzer] Reland "SetThreadName windows implementation" (#83562)
Following-up on GH-76761.
Commit: 26fa4409572ad81c5522165ba2a831845f4d0635
https://github.com/llvm/llvm-project/commit/26fa4409572ad81c5522165ba2a831845f4d0635
Author: Amara Emerson <amara at apple.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
Log Message:
-----------
[GlobalISel] Fix yet another pointer type invalid combining issue, this time in tryFoldSelectOfConstants()
Commit: b408241d0ad9ce009b49018fe1e9838887abf3c1
https://github.com/llvm/llvm-project/commit/b408241d0ad9ce009b49018fe1e9838887abf3c1
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
Log Message:
-----------
[compiler-rt] adding fchmodat2 syscall introduced in Linux 6.6. (#82275)
Commit: 5bb06429d9fdedc5f13f20faedf0edd33243342a
https://github.com/llvm/llvm-project/commit/5bb06429d9fdedc5f13f20faedf0edd33243342a
Author: Florian Mayer <fmayer at google.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
A bolt/test/X86/linux-alt-instruction.s
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/include/clang/InstallAPI/Frontend.h
M clang/include/clang/InstallAPI/Visitor.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/InstallAPI/Frontend.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseExpr.cpp
A clang/test/CodeGen/attr-availability-visionos.c
A clang/test/CodeGen/tbaa-struct-relaxed-aliasing-with-tsan.cpp
M clang/test/Driver/cuda-phases.cu
A clang/test/InstallAPI/functions.test
A clang/test/Sema/attr-availability-visionos.c
M clang/tools/clang-installapi/Options.cpp
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
M clang/unittests/Interpreter/CMakeLists.txt
A clang/unittests/Interpreter/IncrementalCompilerBuilderTest.cpp
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
M cross-project-tests/debuginfo-tests/llgdb-tests/static-member-2.cpp
M cross-project-tests/debuginfo-tests/llgdb-tests/static-member.cpp
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/c23.rst
M libc/docs/index.rst
M libc/docs/math/stdfix.rst
A libc/docs/talks.rst
M libc/spec/llvm_libc_stdfix_ext.td
M libc/src/__support/CPP/bit.h
M libc/src/__support/UInt.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdbit/stdc_count_ones_uc.cpp
M libc/src/stdbit/stdc_count_ones_ui.cpp
M libc/src/stdbit/stdc_count_ones_ul.cpp
M libc/src/stdbit/stdc_count_ones_ull.cpp
M libc/src/stdbit/stdc_count_ones_us.cpp
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/exphk.cpp
A libc/src/stdfix/exphk.h
A libc/src/stdfix/expk.cpp
A libc/src/stdfix/expk.h
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/ExpTest.h
A libc/test/src/stdfix/exphk_test.cpp
A libc/test/src/stdfix/expk_test.cpp
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/test/API/lang/c/tls_globals/TestTlsGlobals.py
M lldb/test/Shell/Unwind/eh-frame-dwarf-unwind.test
M lldb/test/Shell/Unwind/thread-step-out-ret-addr-check.test
M lldb/test/Shell/lit.cfg.py
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/TextAPI/Record.h
M llvm/include/llvm/TextAPI/RecordsSlice.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/TextAPI/RecordsSlice.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/iabs.ll
A llvm/test/CodeGen/RISCV/pr84200.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
A llvm/test/CodeGen/X86/GlobalISel/legalize-sdiv.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-srem.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-udiv.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir
R llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
A llvm/test/CodeGen/X86/isel-sdiv.ll
A llvm/test/CodeGen/X86/isel-srem.ll
A llvm/test/CodeGen/X86/isel-udiv.ll
A llvm/test/CodeGen/X86/isel-urem.ll
M llvm/test/Transforms/CorrelatedValuePropagation/urem-expansion.ll
M llvm/unittests/TextAPI/RecordTests.cpp
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
M mlir/include/mlir/Dialect/CMakeLists.txt
M mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
A mlir/include/mlir/Dialect/XeGPU/CMakeLists.txt
A mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
A mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/InitAllDialects.h
M mlir/lib/Dialect/CMakeLists.txt
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
A mlir/lib/Dialect/XeGPU/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
A mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/2233432a54c5...5bb06429d9fd
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