[all-commits] [llvm/llvm-project] 909ab0: [RISCV] Insert a freeze before converting select t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 909ab0e0d1903ad2329ca9fdf248d21330f9437f
      https://github.com/llvm/llvm-project/commit/909ab0e0d1903ad2329ca9fdf248d21330f9437f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-07 (Thu, 07 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    A llvm/test/CodeGen/RISCV/pr84200.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/signed-truncation-check.ll

  Log Message:
  -----------
  [RISCV] Insert a freeze before converting select to AND/OR. (#84232)

Select blocks poison, but AND/OR do not. We need to insert a freeze
to block poison propagation.

This creates suboptimal codegen which I will try to fix with other
patches. I'm prioritizing the correctness fix since we have 2 bug reports.

Fixes #84200 and #84350



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications