[all-commits] [llvm/llvm-project] fc9f1d: [mlir][sparse] use a consistent order between [dis...

[Peiming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fc9f1d49aae4328ef36e1d9ba606e93703fde970
      https://github.com/llvm/llvm-project/commit/fc9f1d49aae4328ef36e1d9ba606e93703fde970
  Author: Peiming Liu <peiming at google.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
    M mlir/test/Dialect/SparseTensor/GPU/gpu_spgemm_lib.mlir
    M mlir/test/Dialect/SparseTensor/external.mlir
    M mlir/test/Dialect/SparseTensor/invalid.mlir
    M mlir/test/Dialect/SparseTensor/pack_copy.mlir
    M mlir/test/Dialect/SparseTensor/roundtrip.mlir
    M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
    M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
    M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir
    M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack_d.mlir

  Log Message:
  -----------
  [mlir][sparse] use a consistent order between [dis]assembleOp and sto… (#84079)

…rage layout.



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