[all-commits] [llvm/llvm-project] d3df2a: [C++20] [Modules] Handle transitive import in the ...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Wed Mar 6 09:28:10 PST 2024
Branch: refs/heads/users/MaskRay/spr/elf-reject-error-prone-meta-characters-in-input-section-description
Home: https://github.com/llvm/llvm-project
Commit: d3df2a834cf6febb44c699d109b9e7f622194837
https://github.com/llvm/llvm-project/commit/d3df2a834cf6febb44c699d109b9e7f622194837
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Module.h
M clang/lib/Basic/Module.cpp
M clang/lib/Sema/SemaModule.cpp
A clang/test/Modules/transitive-import.cppm
Log Message:
-----------
[C++20] [Modules] Handle transitive import in the module properly
Close https://github.com/llvm/llvm-project/issues/84002
Per [module.import]p7:
> Additionally, when a module-import-declaration in a module unit of
> some module M imports another module unit U of M, it also imports all
> translation units imported by non-exported module-import-declarations
> in the module unit purview of U.
However, we only tried to implement it during the implicit import of
primary module interface for module implementation unit.
Also we didn't implement the last sentence from [module.import]p7
completely:
> These rules can in turn lead to the importation of yet more
> translation units.
This patch tries to care the both issues.
Commit: bec7ad9fd6bceb6521448b24faddb01bc52de3a7
https://github.com/llvm/llvm-project/commit/bec7ad9fd6bceb6521448b24faddb01bc52de3a7
Author: Luke Lau <luke at igalia.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
Log Message:
-----------
[RISCV] Add tests for vw{add,sub,mul} with nested extend. NFC
These test cases show (op (ext a), (ext b)) patterns where the dest EEW is
more than 2 * source EEW. These could be lowered into widening ops where we
still have extend the operands, but at a smaller EEW.
Commit: 7a0acccd81df268dc7ad4c0358c42552789f19b4
https://github.com/llvm/llvm-project/commit/7a0acccd81df268dc7ad4c0358c42552789f19b4
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
A clang/test/CXX/drs/dr438.cpp
A clang/test/CXX/drs/dr439.cpp
A clang/test/CXX/drs/dr441.cpp
A clang/test/CXX/drs/dr462.cpp
A clang/test/CXX/drs/dr492.cpp
M clang/test/CXX/drs/dr4xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add some CodeGen tests for CWG 4xx issues (#83715)
This patch covers the following defect reports:
[CWG438](https://cplusplus.github.io/CWG/issues/438.html) "Possible flaw
in wording for multiple accesses to object between sequence points",
[CWG439](https://cplusplus.github.io/CWG/issues/439.html) "Guarantees on
casting pointer back to cv-qualified version of original type",
[CWG441](https://cplusplus.github.io/CWG/issues/441.html) "Ordering of
static reference initialization",
[CWG462](https://cplusplus.github.io/CWG/issues/462.html) "Lifetime of
temporaries bound to comma expressions",
[CWG492](https://cplusplus.github.io/CWG/issues/492.html) "`typeid`
constness inconsistent with example".
[CWG475](https://cplusplus.github.io/CWG/issues/475.html) "When is
`std::uncaught_exception()` true? (take 2)" requires a libc++abi test.
As for [CWG454](https://cplusplus.github.io/CWG/issues/454.html) "When
is a definition of a static data member required?", I don't feel
confident in my understanding of it, so skipping over it.
Commit: 9f45c5e1a65a1abf4920b617d36ed05e73c04bea
https://github.com/llvm/llvm-project/commit/9f45c5e1a65a1abf4920b617d36ed05e73c04bea
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Fix infinite loop in select equivalence fold (#84036)
When replacing with a non-constant, it's possible that the result of the
simplification is actually more complicated than the original, and may
result in an infinite combine loop.
Mitigate the issue by requiring that either the replacement or
simplification result is constant, which should ensure that it's
simpler. While this check is crude, it does not appear to cause
optimization regressions in real-world code in practice.
Fixes https://github.com/llvm/llvm-project/issues/83127.
Commit: 6cdf596c52f028ea7d150e0696f967fbff443ccf
https://github.com/llvm/llvm-project/commit/6cdf596c52f028ea7d150e0696f967fbff443ccf
Author: hanbeom <kese111 at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/InstCombine/phi-select-constant.ll
M llvm/test/Transforms/InstCombine/pr63791.ll
M llvm/test/Transforms/InstCombine/sink_to_unreachable.ll
M llvm/test/Transforms/InstCombine/unreachable-code.ll
Log Message:
-----------
[InstCombine] If inst in unreachable refers to an inst change it to poison (#78444)
Instructions in unreachable basic blocks are removed, but terminators
are not. In this case, even instructions that are only referenced by
a terminator, such as a return instruction, cannot be processed
properly.
This patch changes the operand of a return instruction in an
unreachable basic block to poison if it refers to the instruction,
allowing the instruction to be properly processed.
Fixes #65107.
Commit: aced81c0a5bf30dda99fde2e28364426de4c18d3
https://github.com/llvm/llvm-project/commit/aced81c0a5bf30dda99fde2e28364426de4c18d3
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/C/C2x/n3018.c
A clang/test/Parser/c23-constexpr.c
A clang/test/Sema/constexpr.c
M clang/www/c_status.html
Log Message:
-----------
[C23] Implement N3018: The constexpr specifier for object definitions (#73099)
The implementation mostly reuses C++ code paths where possible,
including narrowing check in order to provide diagnostic messages in
case initializer for constexpr variable is not exactly representable in
target type.
The following won't work due to lack of support for other features:
- Diagnosing of underspecified declarations involving constexpr
- Constexpr attached to compound literals
Also due to lack of support for char8_t some of examples with utf-8
strings don't work properly.
Fixes https://github.com/llvm/llvm-project/issues/64742
Commit: 6e27dd47e1fc17cf661b568901fe7392ed1b8f2b
https://github.com/llvm/llvm-project/commit/6e27dd47e1fc17cf661b568901fe7392ed1b8f2b
Author: Ingo MĂźller <ingomueller at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
Log Message:
-----------
[mlir][gpu] Replace MLIR_GPU_TO_HSACO_PASS_ENABLE by more generic one. (#84001)
This is another follow-up of #83004. The PR replaces the macro
`MLIR_GPU_TO_HSACO_PASS_ENABLE` with the more generic macro
`MLIR_ENABLE_ROCM_CONVERSIONS`. Until now, the former has been defined
if and only if the latter evaluated to true in CMake. However, the
former was not defined when the latter evaluated to false, in which case
a warning was raised if compiled with `-Wundef`. Using a single macro
relies on the `#cmakedefine01` mechanism that ensures the macro is
always set to either 0 or 1.
Commit: d70254a623d7c23c493cc793756a5a9d758b0a14
https://github.com/llvm/llvm-project/commit/d70254a623d7c23c493cc793756a5a9d758b0a14
Author: Ingo MĂźller <ingomueller at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][nvvm] Add missing include to llvm-config.h. (#83998)
This is another follow-up of #83004. `NVVM/Target.cpp` uses the macro
`MLIR_NVPTXCOMPILER_ENABLED`, which is defined in `llvm-config.h` but
did not include that file, yielding a warning when compiled with
`-Wundef`. This PR adds the include.
~~This is another follow-up of #83004, which made the same change for
`MLIR_CUDA_CONVERSIONS_ENABLED`. As the previous PR, this PR commit
exposes mentioned CMake variable through `mlir-config.h` and uses the
macro that is introduced with the same name. This replaces the macro
`MLIR_NVPTXCOMPILER_ENABLED`, which the CMake files previously defined
manually.~~
Commit: 0e5bde021252f68b378b31fd64a885a8b28aad65
https://github.com/llvm/llvm-project/commit/0e5bde021252f68b378b31fd64a885a8b28aad65
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributeInterfaces.h
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
Log Message:
-----------
[mlir] Remove noexcept again from move constructors.
LLVM does not have the corresponding ClangTidy check enabled, so we
should not be fixing such findings.
Commit: 52d5b8e02d258e4c32864eb1bb943cfae119b1d6
https://github.com/llvm/llvm-project/commit/52d5b8e02d258e4c32864eb1bb943cfae119b1d6
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
Log Message:
-----------
[AMDGPU] Don't form sext/abs/neg fp8 cvt (#83843)
gfx940 does not allow abs/sext/neg on v_cvt_fp8/bf8 & pk variants.
Fixes SWDEV-447468
Commit: 471a6128901747130ae11ce87b6e0095f862ed9a
https://github.com/llvm/llvm-project/commit/471a6128901747130ae11ce87b6e0095f862ed9a
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/test/mlir-tblgen/rewriter-errors.td
M mlir/tools/mlir-tblgen/RewriterGen.cpp
Log Message:
-----------
[mlir][drr] Add warning for simple case of mismatched variadic. (#84040)
When a variadic argument is expected but not provided the compilation
fails later with a difficult to follow compilation error. Add a simple
check to catch one such case.
This is not yet general as it doesn't yet check leaf nodes.
Commit: ac74d9ec0f73898713dd6e0d33f148c13a51875d
https://github.com/llvm/llvm-project/commit/ac74d9ec0f73898713dd6e0d33f148c13a51875d
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/Sema.cpp
Log Message:
-----------
[clang][NFC] Regroup declarations in `Sema` (#82217)
This patch regroups declarations in `Sema` based on the file they are
implemented in (e.g. `SemaChecking.cpp`). This allows to logically split
`Sema` in 42 groups. No physical separation is done (e.g. splitting
`Sema` into multiple classes). Table of contents added at the very
beginning of `Sema`. Grouping is reflected in Doxygen commands, so
structure of API reference of `Sema` is also significantly improved
([example from official
documentation](https://www.doxygen.nl/manual/examples/memgrp/html/class_memgrp___test.html),
[comparison of Sema API
reference](https://github.com/llvm/llvm-project/pull/82217#issuecomment-1954567763)).
While grouping is intentional, as well as each group consisting of
`public` declarations followed by `private` ones (without changing
access in-between), exact contents and order of declarations of each
group is partially carried over from old structure, partially accidental
due to time constrains to do the regrouping over the weekend (`Sema` is
just enormously big). Data members and inline function definitions in
`Sema.h` complicate the matter, since it's not obvious which group they
belong to. Further work is expected to refine contents and order of
declarations.
What is also intentional is some kind of layering, where Concepts group
follows template groups, and ObjC, code completion, CUDA, HLSL, OpenACC,
OpenMP, and SYCL are all placed at the end of the file, after C and C++
parts of `Sema`.
I used `clang-query` to verify that access specifiers were preserved
during the process (https://gcc.godbolt.org/z/9johffY9T, thank you
@ilya-biryukov). Only the following 3 member types were converted from
`private` to `public` because of limitations of the new grouping:
`DeclareTargetContextInfo`, `TypoExprState`, `SatisfactionStackEntryTy`.
Member initializer list of `Sema` in `Sema.cpp` is rewritten to reflect
new order of data members in order to avoid `-Wreorder-ctor`.
Since this patch touches almost every line in `Sema.h`, it was
considered appropriate to run clang-format on the whole file, and not
just on changed lines.
Commit: 20459ddc82514249501c3517583c4ec8dd23cecd
https://github.com/llvm/llvm-project/commit/20459ddc82514249501c3517583c4ec8dd23cecd
Author: Jonathan Schilling <130992531+jons-pf at users.noreply.github.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M openmp/tools/archer/ompt-tsan.cpp
Log Message:
-----------
[openmp] Clarify error message if TSan is missing (#70916)
For an uninformed user, the error message might refer to a missing "TSan
stopping operation", rather than indicating that TSan is missing **and
therefore** operation is stopped.
Commit: 92529eb4aeb2dbb706aedebc1ed9fc4f8045231a
https://github.com/llvm/llvm-project/commit/92529eb4aeb2dbb706aedebc1ed9fc4f8045231a
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CodeGen/attr-target-version.c
M clang/test/Sema/attr-target-version.c
Log Message:
-----------
[FMV] Allow target version definitions in any order. (#83887)
This patch fixes #71698. It allows defining the default target version
prior to other version definitions without raising semantic errors.
Commit: e85470232ba2fa49aaee83240741de0bc82a3ffa
https://github.com/llvm/llvm-project/commit/e85470232ba2fa49aaee83240741de0bc82a3ffa
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
Subscribe @Endilll to changes in Clang's `Sema.h`
Commit: 239312e49b2fdf35e23d75197a621ee6087743ee
https://github.com/llvm/llvm-project/commit/239312e49b2fdf35e23d75197a621ee6087743ee
Author: Alejandro Ălvarez AyllĂłn <alejandro.alvarez at sonarsource.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/Inputs/system-header-simulator-for-simple-stream.h
M clang/test/Analysis/Inputs/system-header-simulator-for-valist.h
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/stream-invalidate.c
M clang/test/Analysis/stream.c
Log Message:
-----------
Reapply "[clang][analyzer] StreamChecker: Model getc, vfscanf, putc, vfprintf" (#83281)
`va_list` is a platform-specific type. On some, it is a struct instead
of a pointer to a struct, so `lookupFn` was ignoring calls to `vfprintf`
and `vfscanf`.
`stream.c` now runs in four different platforms to make sure the logic
works across targets.
Commit: ea23761429faa4e61d7a601da9a313dfdc058cb0
https://github.com/llvm/llvm-project/commit/ea23761429faa4e61d7a601da9a313dfdc058cb0
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/test/CodeGen/AArch64/ldp-stp-unknown-size.mir
Log Message:
-----------
[AArch64] Verify ldp/stp alignment stricter (#84124)
When ldp-aligned-only/stp-aligned-only is specified, modified to cancel
ldp/stp transformation if MachineMemOperand is not present or the access
size is unknown.
In the previous implementation, the test passed when there was no
MachineMemOperand. Also, if the size was unknown, an incorrect value was
used or an assertion failed. (But actually, if there is no
MachineMemOperand, it will be excluded from the target by
isCandidateToMergeOrPair() before reaching the part.)
A statistic NumFailedAlignmentCheck is added. NumPairCreated is modified
so that it only counts if it is not canceled.
Commit: 86b630092f9a5139c4c4d627f1e0504e8f549bce
https://github.com/llvm/llvm-project/commit/86b630092f9a5139c4c4d627f1e0504e8f549bce
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Allow getFieldPtr ops on null pointers in C
Commit: a9ff5c0b75abc3b7aa5c357b226e067b4ddc04bf
https://github.com/llvm/llvm-project/commit/a9ff5c0b75abc3b7aa5c357b226e067b4ddc04bf
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/CodeOwners.rst
Log Message:
-----------
[clang][Docs] Add my Discourse + Discord name
And escape the @ in my email
Commit: 5ddc5b8525a9256716cda1398249f0ab2dd968eb
https://github.com/llvm/llvm-project/commit/5ddc5b8525a9256716cda1398249f0ab2dd968eb
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
Log Message:
-----------
[mlir][emitc] Fix `emitc.expression` example (#84060)
Make it use and refer to `emitc.yield` and also fix type issues.
Commit: cf922e51b850410a3a2944035432f44f1e741b21
https://github.com/llvm/llvm-project/commit/cf922e51b850410a3a2944035432f44f1e741b21
Author: Yingchi Long <i at lyc.dev>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMCInstLower.cpp
Log Message:
-----------
[BPF] lowering target address leaf nodes tconstpool (#73667)
Adds custom lowering for tconstpool.
Please ref: https://github.com/llvm/llvm-project/pull/73668 for test
coverage
Commit: 716a23c412704c0224bbe97c1a55ced1b1624e0c
https://github.com/llvm/llvm-project/commit/716a23c412704c0224bbe97c1a55ced1b1624e0c
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/docs/Status/SpaceshipPapers.csv
Log Message:
-----------
[libc++][NFC] Status page: fix minor formatting issues (#83969)
Fixes several minor formatting issues and omissions I introduced on the
status pages in previous patches.
Commit: c2e34a60c433f5dff79c4c2bdb2df5d8ad1f201f
https://github.com/llvm/llvm-project/commit/c2e34a60c433f5dff79c4c2bdb2df5d8ad1f201f
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M lldb/tools/lldb-server/lldb-gdbserver.cpp
Log Message:
-----------
[lldb][lldb-server] Fix pipe spelling mistake in log message
Commit: a888f5e4d7d979617a47262a875f5433ee161074
https://github.com/llvm/llvm-project/commit/a888f5e4d7d979617a47262a875f5433ee161074
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/test/MC/AMDGPU/bf16_imm.s
M llvm/test/MC/AMDGPU/gfx1150_asm_features.s
M llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
M llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_exp.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_global_load_tr.s
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mtbuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mtbuf_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vdsdir.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vsample.s
M llvm/test/MC/AMDGPU/gfx12_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx12_asm_wmma_w64.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_salu_float.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_global_load_tr.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mtbuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vdsdir.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vinterp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w32.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w64.txt
Log Message:
-----------
[AMDGPU][NFC] Update tests to use -triple= instead of -arch=. (#84153)
Commit: df267fe32759658bebd846f98fdf5db61312837d
https://github.com/llvm/llvm-project/commit/df267fe32759658bebd846f98fdf5db61312837d
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
Log Message:
-----------
[mlir][EmitC] Correct comment (NFC)
Commit: a6ee0adb724a3f1705fc54937e734ffc2a032096
https://github.com/llvm/llvm-project/commit/a6ee0adb724a3f1705fc54937e734ffc2a032096
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/MCA/Stages/InOrderIssueStage.cpp
A llvm/test/tools/llvm-mca/AMDGPU/carried-over.s
Log Message:
-----------
[llvm-mca][AMDGPU] Retire instructions that have issue carry over correctly (#83881)
https://github.com/llvm/llvm-project/issues/83775 shows llvm-mca hits
sanitizer error in cycleEnd. There was an instruction that takes
multiple cycles to issue and is finished executing directly after issue.
Prior to this patch, the instruction is retired on the first issue
cycle, despite taking multiple cycles to issue.
To fix this, if an instruction takes multiple cycles to issue and is
done executing after issue, let updateCarriedOver retire the instruction
when it is fully issued.
Commit: c486d90bdcbd50046fbd8ac874e4b0e62e287193
https://github.com/llvm/llvm-project/commit/c486d90bdcbd50046fbd8ac874e4b0e62e287193
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CheckerDocumentation.cpp
Log Message:
-----------
[analyzer][NFC] Document check::ASTCodeBody checker callback (#84160)
Fixes #73764
With this patch, now all the callbacks are demonstrated here.
Commit: be15a6b3b68bed7b9d982f25b2e10a273302002a
https://github.com/llvm/llvm-project/commit/be15a6b3b68bed7b9d982f25b2e10a273302002a
Author: Ingo MĂźller <ingomueller at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][opt] Expose MLIR_ENABLE_DEPRECATED_GPU_SER... in mlir-config.h. (#84006)
This is another follow-up of #83004, which made the same change for
`MLIR_CUDA_CONVERSIONS_ENABLED`. As the previous PR, this PR commit
exposes mentioned CMake variable through `mlir-config.h` and uses the
macro that is introduced with the same name. This replaces the macro
`MLIR_ENABLE_DEPRECATED_GPU_SERIALIZATION`, which the CMake files
previously defined manually.
Commit: 099045a0456a77c38aed504d0b50d44c4d3df6ff
https://github.com/llvm/llvm-project/commit/099045a0456a77c38aed504d0b50d44c4d3df6ff
Author: Ingo MĂźller <ingomueller at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][nvvm] Expose MLIR_NVPTXCOMPILER_ENABLED in mlir-config.h. (#84007)
This is another follow-up of #83004, which made the same change for
`MLIR_CUDA_CONVERSIONS_ENABLED`. As the previous PR, this PR commit
exposes mentioned CMake variable through `mlir-config.h` and uses the
macro that is introduced with the same name. This replaces the macro
`MLIR_NVPTXCOMPILER_ENABLED`, which the CMake files previously defined
manually.
Commit: 8406f8023dc08a1697acd2375e120670c0233a8a
https://github.com/llvm/llvm-project/commit/8406f8023dc08a1697acd2375e120670c0233a8a
Author: Ingo MĂźller <ingomueller at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/include/mlir/Config/mlir-config.h.cmake
Log Message:
-----------
[mlir][cmake] Enable -Wundef. (#84011)
This is another follow-up of #83004, which fixed a bug due to some
macros not being defined in some situations. By raising warnings on
undefined macros, this kind of bug is less likely to be introduced.
Similar to #83004, the fix is probably adding an include to
`mlir-config.h` (and potentially defining the macro there).
Commit: 38763be6ab706e5661e94b68c3aa2069f4c736d8
https://github.com/llvm/llvm-project/commit/38763be6ab706e5661e94b68c3aa2069f4c736d8
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M flang/include/flang/Evaluate/traverse.h
M flang/lib/Evaluate/tools.cpp
M flang/test/Semantics/forall01.f90
M flang/test/Semantics/selecttype03.f90
Log Message:
-----------
[flang] Do not traverse selectors in FindImpureCall and HasVectorSubscript (#84041)
In presence of symbols with AssocEntityDetails in an expression,
`Traverse`, `AnyTraverse`, `AllTraverse`, and `SetTraverse`
automatically visit the selector expression or variable.
This is most often the desired behavior but can be surprising, and was
not correct for FindImpureCall and HasVectorSubscript.
Add a default template option to flag the behavior to someone willing to
use the Traverse helper for a new utility, and set this template to
false for FindImpureCall and HasVectorSubscript.
Commit: c4979c935f778eca623afd17dad6f97facba34bf
https://github.com/llvm/llvm-project/commit/c4979c935f778eca623afd17dad6f97facba34bf
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][VectorOps] Add fold vector.shuffle -> vector.interleave (#80968)
This folds fixed-size vector.shuffle ops that perform a 1-D interleave
to a vector.interleave operation.
For example:
```mlir
%0 = vector.shuffle %a, %b [0, 2, 1, 4] : vector<2xi32>, vector<2xi32>
```
folds to:
```mlir
%0 = vector.interleave %a, %b : vector<2xi32>
```
Depends on: #80967
Commit: e9c1dbb408c51115289a135e721de0bf5efec0c1
https://github.com/llvm/llvm-project/commit/e9c1dbb408c51115289a135e721de0bf5efec0c1
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
Log Message:
-----------
Revert "[AMDGPU] Replace `isInlinableLiteral16` with specific version (#81345)"
This reverts commit 530f0e64ec11327879c44f2fd55c7c28efdbaa2d because it breaks
downstream.
Commit: 33e312137b065ba330b187f56ddd60df70927241
https://github.com/llvm/llvm-project/commit/33e312137b065ba330b187f56ddd60df70927241
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/www/cxx_dr_status.html
M clang/www/cxx_status.html
M clang/www/make_cxx_dr_status
Log Message:
-----------
[Clang] Mark papers & core issues implemented in clang 18 as released
Commit: ae79854e4dcfb923130d3cd751363dbee19cb5b5
https://github.com/llvm/llvm-project/commit/ae79854e4dcfb923130d3cd751363dbee19cb5b5
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
Update C status page now that Clang 18.x is released
Commit: a8dd99eb36bbf000bb1b42e27df8644eb0762fb8
https://github.com/llvm/llvm-project/commit/a8dd99eb36bbf000bb1b42e27df8644eb0762fb8
Author: eric <eric at efcs.ca>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M libcxx/utils/ci/docker-compose.yml
Log Message:
-----------
Bump the github actions runner base version.
Yesterday, one of the issues the libc++ builders encountered was that
they were using a client that was too old; too old to even update
automatically.
To get things working, i had to push a testing image with this change.
The testing image has been working for 12 hours now, so it's time to
commit to it :-)
Commit: 63afcbbeeaf68751b57acc1f2911afee767d86bb
https://github.com/llvm/llvm-project/commit/63afcbbeeaf68751b57acc1f2911afee767d86bb
Author: Botond IstvĂĄn HorvĂĄth <horvath.botond.istvan at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CXX/drs/dr24xx.cpp
M clang/test/SemaCXX/overload-template.cpp
M clang/test/SemaCXX/overloaded-operator.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang][Sema] Bugfix for choosing the more specialized overload (#83279)
There was a bug in Clang where it couldn't choose which overload
candidate was more specialized if it was comparing a member-function to
a non-member function. Previously, this was detected as an ambiguity,
now Clang chooses correctly.
This patch fixes the bug by fully implementing CWG2445 and moving the
template transformation described in `[temp.func.order]` paragraph 3
from `isAtLeastAsSpecializedAs()` to
`Sema::getMoreSpecializedTemplate()` so we have the transformed
parameter list during the whole comparison. Also, to be able to add the
correct type for the implicit object parameter
`Sema::getMoreSpecializedTemplate()` has new parameters for the object
type.
Fixes #74494, fixes #82509
Commit: 1fc5e50cebf1e423bce105930c3a075044998f68
https://github.com/llvm/llvm-project/commit/1fc5e50cebf1e423bce105930c3a075044998f68
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
A llvm/test/CodeGen/AMDGPU/fpenv.ll
Log Message:
-----------
[AMDGPU] Implement 'llvm.get.fpenv' and 'llvm.set.fpenv' (#83906)
Summary:
This patch implements the LLVM floating point environment control
intrinsics and also exposes it through clang. We encode the floating
point environment as a 64-bit value that simply concatenates the values
of the mode registers and the current trap status. We only fetch the
bits relevant for floating point instructions. That is, rounding mode,
denormalization mode, ieee, dx10 clamp, debug, enabled traps, f16
overflow, and active exceptions.
Commit: 6d3bb854713e43daad34ffc84d0132d7fe010abf
https://github.com/llvm/llvm-project/commit/6d3bb854713e43daad34ffc84d0132d7fe010abf
Author: Sandeep Kosuri <66305775+sandeepkosuri at users.noreply.github.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/declare_target_ast_print.cpp
M clang/test/OpenMP/declare_target_messages.cpp
Log Message:
-----------
[OpenMP] Parse and Sema support for declare target in local scope (#83223)
- adds Parse and Sema support for the `declare target` directive inside
a function scope.
Commit: f7d354af5714358d7ad83e58a1016c3f385416dd
https://github.com/llvm/llvm-project/commit/f7d354af5714358d7ad83e58a1016c3f385416dd
Author: yandalur <quic_yandalur at quicinc.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
A llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
Log Message:
-----------
[Hexagon] Fix shift value when folding shl DAG node (#83853)
When folding (or (shl xx, s), (zext y)) to (COMBINE (shl xx, s-32), y),
fix resulting shift value in HexagonISD::COMBINE node to not generate
negative values.
---------
Co-authored-by: Yashas Andaluri <yandalur at qti.qualcomm.com>
Commit: 8fdec5d3badb94807d757c0c58a3900704320919
https://github.com/llvm/llvm-project/commit/8fdec5d3badb94807d757c0c58a3900704320919
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/include/llvm/Support/Casting.h
M llvm/unittests/Support/Casting.cpp
Log Message:
-----------
[Support][Casting] Add predicates for `isa*` functions (#83753)
Expose function objects that call into `llvm::isa` and
`llvm::isa_and_present`, such that these type checks can be used as
predicates in generic algorithms.
Before this change, `llvm::isa*` functions cannot be easily used without
knowing both the argument type and the checked types, which leads to
them being wrapped in lambdas. For example:
```c++
llvm::all_of(myTypes,
[](auto type) { return llvm::isa<VectorType>(type); });
```
With this PR the example above becomes:
```c++
llvm::all_of(myTypes, llvm::IsaPred<VectorType>);
```
As an alternative solution, I considered redefining `isa*` as function
objects, but I decided against doing that because it would create
asymmetry with other cast *functions* and could break code that depends
on them being actual functions.
Commit: 4490003a22658dcd12527029b2c8682b63d8a9d6
https://github.com/llvm/llvm-project/commit/4490003a22658dcd12527029b2c8682b63d8a9d6
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenHIP/default-attributes.hip
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M lld/test/ELF/lto/amdgcn-oses.ll
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/Bitcode/upgrade-module-flag.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-func.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-asan.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/tools/llvm-reduce/reduce-module-flags.ll
Log Message:
-----------
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
The previous name 'amdgpu_code_object_version', was misleading since
this is really a property of the HSA OS. The new spelling also matches
the asm directive I added in bc82cfb.
Commit: fec471649fffaa3ec44e17801e5c9605825e58bb
https://github.com/llvm/llvm-project/commit/fec471649fffaa3ec44e17801e5c9605825e58bb
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/Sema/SemaTemplate.cpp
Log Message:
-----------
[clang] Use getDefaultArgRange instead of getDefaultArg to retrieve the (#79296)
source location in` AliasTemplateDeductionGuideTransform`.
I don't have a reproducible testcase, but this should be a safe and
non-functional change. We have checked the `hasDefaultArg` before
calling `getDefaultArg()`, but `hasDefaultArg` allows
unparsed/uninstantiated default arg which is prohibited in
`getDefaultArg()`.
Since we're only interested in the source location, we switch to use
`getDefaultArgRange()` API.
Commit: f448b8ec03bbd0e1b47d56f461b324fb2af8c113
https://github.com/llvm/llvm-project/commit/f448b8ec03bbd0e1b47d56f461b324fb2af8c113
Author: Joe Nash <Sisyph at users.noreply.github.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
Log Message:
-----------
[AMDGPU] Make gfx11 vop1 disassembler tests use strict-whitespace (#84078)
NFC.
The whitespace needs to be consistently formatted in some manner. Might
as well use -strict-whitespace as the standard.
Adds -strict-whitespace to RUN lines and adjust CHECK line space padding
accordingly.
Also test REAL16 and FAKE16 CHECK lines with wave64.
Commit: a87dc23a6271cadd6d3f93561f2d8b1661399e6d
https://github.com/llvm/llvm-project/commit/a87dc23a6271cadd6d3f93561f2d8b1661399e6d
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/include/clang/AST/DeclOpenMP.h
M clang/include/clang/AST/ParentMapContext.h
M clang/include/clang/Basic/OpenCLExtensionTypes.def
M clang/include/clang/Basic/RISCVVTypes.def
M clang/include/clang/Basic/arm_neon_incl.td
M clang/include/clang/Serialization/PCHContainerOperations.h
M clang/include/clang/StaticAnalyzer/Core/PathDiagnosticConsumers.h
M clang/lib/ARCMigrate/TransGCAttrs.cpp
M clang/lib/AST/Interp/ByteCodeEmitter.h
M clang/lib/AST/Interp/FunctionPointer.h
M clang/lib/AST/Interp/PrimType.h
M clang/lib/Driver/ToolChains/Arch/Mips.h
M clang/lib/Driver/ToolChains/Arch/Sparc.h
M clang/lib/Headers/llvm_libc_wrappers/assert.h
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/StaticAnalyzer/Checkers/DirectIvarAssignment.cpp
M clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/STLAlgorithmModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
M clang/test/Analysis/misc-ps-region-store.mm
M clang/test/Rewriter/rewrite-modern-class.mm
M clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.h
M clang/tools/diagtool/DiagTool.cpp
M clang/unittests/AST/ASTImporterODRStrategiesTest.cpp
M clang/unittests/ASTMatchers/Dynamic/RegistryTest.cpp
M clang/unittests/ASTMatchers/Dynamic/VariantValueTest.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CXXOperatorCallExprTraverser.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksBinaryOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCompoundAssignOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/InitListExprPostOrderNoQueue.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/InitListExprPreOrderNoQueue.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/TemplateArgumentLocTraverser.cpp
Log Message:
-----------
[clang][NFC] Trim license header comments to 81 characters (#82919)
clang-format would format these headers poorly by splitting it into
multiple lines.
Commit: 1fd1f4c0e1f229a2eceb94fc4e41bdd4b9ca7d5a
https://github.com/llvm/llvm-project/commit/1fd1f4c0e1f229a2eceb94fc4e41bdd4b9ca7d5a
Author: Mirko BrkuĹĄanin <Mirko.Brkusanin at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
A llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
Log Message:
-----------
[AMDGPU] Handle amdgpu.last.use metadata (#83816)
Convert !amdgpu.last.use metadata into MachineMemOperand for last use
and handle it in SIMemoryLegalizer similar to nontemporal and volatile.
Commit: ad1b2a812973d584f56121b953bf9698b32386ae
https://github.com/llvm/llvm-project/commit/ad1b2a812973d584f56121b953bf9698b32386ae
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
A clang/test/Analysis/assuming-unsigned-ge-0.c
Log Message:
-----------
[analyzer] Demonstrate superfluous unsigned >= 0 assumption (#78442)
This commit adds a testcase which highlights the current incorrect
behavior of the CSA diagnostic generation: it produces a note which says
"Assuming 'arg' is >= 0" in a situation where this is not a fresh
assumption because 'arg' is an unsigned integer.
I also created ticket 78440 to track this bug.
Commit: f53c2f66a76d8a7dcc649d334cd60374b883196f
https://github.com/llvm/llvm-project/commit/f53c2f66a76d8a7dcc649d334cd60374b883196f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineSetCC - use getZExtOrTrunc() to perform the constant folding. NFCI
Commit: 5a896c66e3074621235a17f9dff95cbbed900c10
https://github.com/llvm/llvm-project/commit/5a896c66e3074621235a17f9dff95cbbed900c10
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Merge repeated getTargetLoweringInfo() calls. NFC.
Commit: 371132962b3566659d533bfe99c3e3cfb0dd37bd
https://github.com/llvm/llvm-project/commit/371132962b3566659d533bfe99c3e3cfb0dd37bd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Log Message:
-----------
[TTI] getInstructionCost - pull out repeated getShuffleMask() calls. NFC.
Pulled out of #84156
Commit: 6540f1635a6566aef93d9b4f568ac648474c39e7
https://github.com/llvm/llvm-project/commit/6540f1635a6566aef93d9b4f568ac648474c39e7
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
A llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[AMDGPU] Add IR-level pass to rewrite away address space 7 (#77952)
This commit adds the -lower-buffer-fat-pointers pass, which is
applicable to all AMDGCN compilations.
The purpose of this pass is to remove the type `ptr addrspace(7)` from
incoming IR. This must be done at the LLVM IR level because `ptr
addrspace(7)`, as a 160-bit primitive type, cannot be correctly handled
by SelectionDAG.
The detailed operation of the pass is described in comments, but, in
summary, the removal proceeds by:
1. Rewriting loads and stores of ptr addrspace(7) to loads and stores of
i160 (including vectors and aggregates). This is needed because the
in-register representation of these pointers will stop matching their
in-memory representation in step 2, and so ptrtoint/inttoptr operations
are used to preserve the expected memory layout
2. Mutating the IR to replace all occurrences of `ptr addrspace(7)` with
the type `{ptr addrspace(8), ptr addrspace(6) }`, which makes the two
parts of a buffer fat pointer (the 128-bit address space 8 resource and
the 32-bit address space 6 offset) visible in the IR. This also impacts
the argument and return types of functions.
3. *Splitting* the resource and offset parts. All instructions that
produce or consume buffer fat pointers (like GEP or load) are rewritten
to produce or consume the resource and offset parts separately. For
example, GEP updates the offset part of the result and a load uses the
resource and offset parts to populate the relevant
llvm.amdgcn.raw.ptr.buffer.load intrinsic call.
At the end of this process, the original mutated instructions are
replaced by their new split counterparts, ensuring no invalidly-typed IR
escapes this pass. (For operations like call, where the struct form is
needed, insertelement operations are inserted).
Compared to LGC's PatchBufferOp (
https://github.com/GPUOpen-Drivers/llpc/blob/32cda89776980202597d5bf4ed4447a1bae64047/lgc/patch/PatchBufferOp.cpp
): this pass
- Also handles vectors of ptr addrspace(7)s
- Also handles function boundaries
- Includes the same uniform buffer optimization for loops and
conditionals
- Does *not* handle memcpy() and friends (this is future work)
- Does *not* break up large loads and stores into smaller parts. This
should be handled by extending the legalization
of *.buffer.{load,store} to handle larger types by producing multiple
instructions (the same way ordinary LOAD and STORE are legalized). That
work is planned for a followup commit.
- Does *not* have special logic for handling divergent buffer
descriptors. The logic in LGC is, as far as I can tell, incorrect in
general, and, per discussions with @nhaehnle, isn't widely used.
Therefore, divergent descriptors are handled with waterfall loops later
in legalization.
As a final matter, this commit updates atomic expansion to treat buffer
operations analogously to global ones.
(One question for reviewers: is the new pass is the right place? Should
it be later in the pipeline?)
Differential Revision: https://reviews.llvm.org/D158463
Commit: 67c6ad6f30e35c7670bce9bca902caa4b1c8c0e8
https://github.com/llvm/llvm-project/commit/67c6ad6f30e35c7670bce9bca902caa4b1c8c0e8
Author: Alejandro Ălvarez AyllĂłn <alejandro.alvarez at sonarsource.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CheckerHelpers.h
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
M clang/test/Analysis/Inputs/system-header-simulator-for-malloc.h
A clang/test/Analysis/getline-alloc.c
Log Message:
-----------
[clang][analyzer] Model allocation behavior or getdelim/geline (#83138)
`getdelim` and `getline` may free, allocate, or re-allocate the input
buffer, ensuring its size is enough to hold the incoming line, the
delimiter, and the null terminator.
`*lineptr` must be a valid argument to `free`, which means it can be
either
1. `NULL`, in which case these functions perform an allocation
equivalent to a call to `malloc` even on failure.
2. A pointer returned by the `malloc` family of functions. Other
pointers are UB (`alloca`, a pointer to a static, to a stack variable, etc.)
Commit: 8e4887ff6de135680512f21fb41e949f73cbf262
https://github.com/llvm/llvm-project/commit/8e4887ff6de135680512f21fb41e949f73cbf262
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M libcxx/include/span
Log Message:
-----------
[libc++][NFC] Remove redundant preprocessor directive
Commit: 12fdabc7908d3acbec42ce6172a225db85cb4f23
https://github.com/llvm/llvm-project/commit/12fdabc7908d3acbec42ce6172a225db85cb4f23
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp] Diagnose dummy pointers used in Inc/Dec ops
For example for unknown parameter decls.
Commit: d9d9301eec6dfefcf53fd04b61324f140f273033
https://github.com/llvm/llvm-project/commit/d9d9301eec6dfefcf53fd04b61324f140f273033
Author: Max Winkler <82551778+MaxEW707 at users.noreply.github.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/warn-self-move.cpp
Log Message:
-----------
[clang][Sema] Warn on self move for inlined static cast (#76646)
There are code bases that inline `std::move` manually via `static_cast`.
Treat a static cast to an xvalue as an inlined `std::move` call and warn
on a self move.
Commit: d4687fe7d1639ea5d16190c89a54de1f2c6e2a9a
https://github.com/llvm/llvm-project/commit/d4687fe7d1639ea5d16190c89a54de1f2c6e2a9a
Author: Exile <2094247798 at qq.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CallEvent.cpp
M clang/test/Analysis/cxx2b-deducing-this.cpp
Log Message:
-----------
[analyzer] Fix crash on dereference invalid return value of getAdjustedParameterIndex() (#83585)
Fixes #78810
Thanks for Snape3058 's comment
---------
Co-authored-by: miaozhiyuan <miaozhiyuan at feysh.com>
Commit: 28e30b4042742bb79cc66b92a16a8508aa35cb92
https://github.com/llvm/llvm-project/commit/28e30b4042742bb79cc66b92a16a8508aa35cb92
Author: ZERO-N <1416312228 at qq.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M clang/lib/Sema/SemaExceptionSpec.cpp
Log Message:
-----------
[Clang][Sema][NFC]Use isa_and_nonnull to simplify the code and avoid build warning (#84181)
Signed-off-by: nwh <nwh_work at foxmail.com>
Commit: 1c6e09c27f2216070abe5c268fb6269aeea97e68
https://github.com/llvm/llvm-project/commit/1c6e09c27f2216070abe5c268fb6269aeea97e68
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/runtime/complex-powi.cpp
A flang/test/Lower/Intrinsics/pow_complex16i.f90
A flang/test/Lower/Intrinsics/pow_complex16k.f90
Log Message:
-----------
[flang] Added COMPLEX(16) ** INTEGER(4/8) lowering and runtime. (#84115)
Commit: 8ee7ef6a373eb36f6945bc5cf0adcb3b94daf120
https://github.com/llvm/llvm-project/commit/8ee7ef6a373eb36f6945bc5cf0adcb3b94daf120
Author: David Green <david.green at arm.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
Log Message:
-----------
[GlobalISel] Use LocationSize in GISelAddressing. NFC (#83885)
This is similar to #83017 but for the areas in GlobalISel's
LoadStoreOpt, and should help simplify #70452 a little. It will likely
change a little again once the sizes can be scalable.
Commit: 571d5af5aa3ebfdf59d2eccb6a90c2b97c6d7ea8
https://github.com/llvm/llvm-project/commit/571d5af5aa3ebfdf59d2eccb6a90c2b97c6d7ea8
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Improve comment on reassociateOps and its helper
Commit: 67c82d6ffb4bbc21212116a11f390761d859297a
https://github.com/llvm/llvm-project/commit/67c82d6ffb4bbc21212116a11f390761d859297a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M clang/lib/Basic/OpenMPKinds.cpp
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/utils/TableGen/DirectiveEmitter.cpp
Log Message:
-----------
[Frontend] Add leaf constructs and association to OpenMP/ACC directives (#83625)
Add members "leafConstructs" and "association" to .td describing
OpenMP/ACC directives. The naming follows the terminology used in the
OpenMP standard: a "leaf" construct is a construct that is itself not a
composition or a combination of other constructs, and "association" is
the source language construct to which the directive applies (e.g. loop,
block, etc.)
The tblgen-generated output then contains two additional functions
- getLeafConstructs(D), and
- getDirectiveAssociation(D)
plus "enum class Association", all in namespaces "llvm::omp" and
"llvm::acc".
Note: getLeafConstructs returns an empty sequence for a construct that
is itself a leaf construct.
Use the new functions to simplify a few OpenMP-related functions in
clang.
Commit: 7755c26195900fa5611cd87582acd2f1875d3c40
https://github.com/llvm/llvm-project/commit/7755c26195900fa5611cd87582acd2f1875d3c40
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll
M llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
M llvm/test/Analysis/ScalarEvolution/add-like-or.ll
M llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll
M llvm/test/Analysis/ScalarEvolution/addrec-sub-nsw.ll
M llvm/test/Analysis/ScalarEvolution/alloca.ll
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll
M llvm/test/Analysis/ScalarEvolution/decrementing_addrecs.ll
M llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll
M llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-select.ll
M llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll
M llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll
M llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
M llvm/test/Analysis/ScalarEvolution/fold.ll
M llvm/test/Analysis/ScalarEvolution/huge-trip-multiple.ll
M llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
M llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll
M llvm/test/Analysis/ScalarEvolution/invalidation.ll
M llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll
M llvm/test/Analysis/ScalarEvolution/load.ll
M llvm/test/Analysis/ScalarEvolution/logical-operations.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll
M llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll
M llvm/test/Analysis/ScalarEvolution/max-expr-cache.ll
M llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll
M llvm/test/Analysis/ScalarEvolution/max-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll
M llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
M llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
M llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
M llvm/test/Analysis/ScalarEvolution/nsw-offset.ll
M llvm/test/Analysis/ScalarEvolution/nsw.ll
M llvm/test/Analysis/ScalarEvolution/outer_phi.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll
M llvm/test/Analysis/ScalarEvolution/pr25369.ll
M llvm/test/Analysis/ScalarEvolution/pr34538.ll
M llvm/test/Analysis/ScalarEvolution/pr48225.ll
M llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
M llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
M llvm/test/Analysis/ScalarEvolution/range-signedness.ll
M llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
M llvm/test/Analysis/ScalarEvolution/ranges.ll
M llvm/test/Analysis/ScalarEvolution/sdiv.ll
M llvm/test/Analysis/ScalarEvolution/sext-add-inreg-loop.ll
M llvm/test/Analysis/ScalarEvolution/sext-mul.ll
M llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll
M llvm/test/Analysis/ScalarEvolution/shift-op.ll
M llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
M llvm/test/Analysis/ScalarEvolution/sle.ll
M llvm/test/Analysis/ScalarEvolution/smax-br-phi-idioms.ll
M llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll
M llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll
M llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll
M llvm/test/Analysis/ScalarEvolution/srem.ll
M llvm/test/Analysis/ScalarEvolution/symbolic_max_exit_count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-minmax.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
M llvm/test/Analysis/ScalarEvolution/trip-count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count10.ll
M llvm/test/Analysis/ScalarEvolution/trip-count12.ll
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
M llvm/test/Analysis/ScalarEvolution/trip-count14.ll
M llvm/test/Analysis/ScalarEvolution/trip-count15.ll
M llvm/test/Analysis/ScalarEvolution/trip-count2.ll
M llvm/test/Analysis/ScalarEvolution/trip-count3.ll
M llvm/test/Analysis/ScalarEvolution/trip-count4.ll
M llvm/test/Analysis/ScalarEvolution/trip-count6.ll
M llvm/test/Analysis/ScalarEvolution/trip-count7.ll
M llvm/test/Analysis/ScalarEvolution/trip-count8.ll
M llvm/test/Analysis/ScalarEvolution/trip-count9.ll
M llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/trip-multiple.ll
M llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll
M llvm/test/Analysis/ScalarEvolution/unknown_phis.ll
M llvm/test/Analysis/ScalarEvolution/widenable-condition.ll
M llvm/test/Transforms/LoopDeletion/invalidate-scev-after-hoisting.ll
M llvm/test/Transforms/LoopSimplify/preserve-scev.ll
Log Message:
-----------
[SCEV] Include type when printing constant max backedge taken count
When printing the result of the analysis, i8 -1 and i64 -1 are quite
different in terms of analysis quality. In a recent conversion with
a new contributor, we ran into exactly this confusion.
Adding the type for constant scevs more globally seems worthwhile, but
introduces a much larger test diff. I'm splitting this off first since
it addresses the immediate need, and then going to do some further
changes to clarify a few related bits of analysis result output.
Commit: c161720ab49ed426e50f70c09da9b0c04be0f50f
https://github.com/llvm/llvm-project/commit/c161720ab49ed426e50f70c09da9b0c04be0f50f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
Log Message:
-----------
[RISCV] Slightly improve expanded multiply emulation in getVLENFactoredAmount. (#84113)
Instead of initializing the accumulator to 0. Initialize it on first
assignment with a mv from the register that holds VLENB << ShiftAmount.
Fix a missing kill flag on the final Add.
I have no real interest in this case, just an easy optimization I
noticed.
Commit: 0cbbcf1ef006ce13a1fa94960067723982ae955a
https://github.com/llvm/llvm-project/commit/0cbbcf1ef006ce13a1fa94960067723982ae955a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M libc/docs/full_cross_build.rst
A libc/docs/gpu/building.rst
M libc/docs/gpu/index.rst
M libc/docs/gpu/rpc.rst
M libc/docs/gpu/using.rst
Log Message:
-----------
[libc] Update GPU documentation pages (#84076)
Summary:
After the overhaul of the GPU build the documentation pages were a
little stale. This updates them with more in-depth information on
building the GPU runtimes and using them. Specifically using them goes
through the differences between the offloading and direct compilation
modes.
Commit: 3589cacfa8da89b9b5051e4dba659caa575e6b3f
https://github.com/llvm/llvm-project/commit/3589cacfa8da89b9b5051e4dba659caa575e6b3f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[ValueTracking] Handle `icmp pred (trunc X), C` in `computeKnownBitsFromCmp` (#82803)
This patch handles the pattern `icmp pred (trunc X), C` in
`computeKnownBitsFromCmp` to infer low bits of `X` from dominating
conditions.
Commit: c371ee9da9c4fa4b682baf47ce5c2a6b6f4c74bc
https://github.com/llvm/llvm-project/commit/c371ee9da9c4fa4b682baf47ce5c2a6b6f4c74bc
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
Log Message:
-----------
[Profile][Windows] Fix flakyness when checking existence of binary id (#84196)
There is a small chance that binary id starting with 0 (1/256). It is
not sufficient to just check the first byte.
Commit: 0bd9255f8ad9f321dd606365e2bc28447a9976cb
https://github.com/llvm/llvm-project/commit/0bd9255f8ad9f321dd606365e2bc28447a9976cb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/psadbw.ll
M llvm/test/CodeGen/X86/sad.ll
Log Message:
-----------
[X86] Improve KnownBits for X86ISD::PSADBW nodes (#83830)
Don't just return the known zero upperbits, compute the absdiff Knownbits and perform the horizontal sum.
Add implementations that handle both the X86ISD::PSADBW nodes and the INTRINSIC_WO_CHAIN intrinsics (pre-legalization).
Commit: f31fc0ba494ad4df1267e0564731482c5b20da05
https://github.com/llvm/llvm-project/commit/f31fc0ba494ad4df1267e0564731482c5b20da05
Author: Fangrui Song <i at maskray.me>
Date: 2024-03-06 (Wed, 06 Mar 2024)
Changed paths:
M .github/CODEOWNERS
M clang/CodeOwners.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclOpenMP.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/ParentMapContext.h
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Module.h
M clang/include/clang/Basic/OpenCLExtensionTypes.def
M clang/include/clang/Basic/RISCVVTypes.def
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_neon_incl.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/PCHContainerOperations.h
M clang/include/clang/StaticAnalyzer/Core/PathDiagnosticConsumers.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CheckerHelpers.h
M clang/lib/ARCMigrate/TransGCAttrs.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Interp/ByteCodeEmitter.h
M clang/lib/AST/Interp/FunctionPointer.h
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/PrimType.h
M clang/lib/Basic/Module.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Arch/Mips.h
M clang/lib/Driver/ToolChains/Arch/Sparc.h
M clang/lib/Headers/llvm_libc_wrappers/assert.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckerDocumentation.cpp
M clang/lib/StaticAnalyzer/Checkers/DirectIvarAssignment.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/STLAlgorithmModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/CallEvent.cpp
M clang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
M clang/test/AST/Interp/c.c
M clang/test/AST/Interp/literals.cpp
M clang/test/Analysis/Inputs/system-header-simulator-for-malloc.h
M clang/test/Analysis/Inputs/system-header-simulator-for-simple-stream.h
M clang/test/Analysis/Inputs/system-header-simulator-for-valist.h
M clang/test/Analysis/Inputs/system-header-simulator.h
A clang/test/Analysis/assuming-unsigned-ge-0.c
M clang/test/Analysis/cxx2b-deducing-this.cpp
A clang/test/Analysis/getline-alloc.c
M clang/test/Analysis/misc-ps-region-store.mm
M clang/test/Analysis/stream-invalidate.c
M clang/test/Analysis/stream.c
A clang/test/C/C2x/n3018.c
M clang/test/CXX/drs/dr24xx.cpp
A clang/test/CXX/drs/dr438.cpp
A clang/test/CXX/drs/dr439.cpp
A clang/test/CXX/drs/dr441.cpp
A clang/test/CXX/drs/dr462.cpp
A clang/test/CXX/drs/dr492.cpp
M clang/test/CXX/drs/dr4xx.cpp
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenHIP/default-attributes.hip
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
A clang/test/Modules/transitive-import.cppm
M clang/test/OpenMP/declare_target_ast_print.cpp
M clang/test/OpenMP/declare_target_messages.cpp
A clang/test/Parser/c23-constexpr.c
M clang/test/Rewriter/rewrite-modern-class.mm
M clang/test/Sema/attr-target-version.c
A clang/test/Sema/constexpr.c
M clang/test/SemaCXX/overload-template.cpp
M clang/test/SemaCXX/overloaded-operator.cpp
M clang/test/SemaCXX/warn-self-move.cpp
M clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.h
M clang/tools/diagtool/DiagTool.cpp
M clang/unittests/AST/ASTImporterODRStrategiesTest.cpp
M clang/unittests/ASTMatchers/Dynamic/RegistryTest.cpp
M clang/unittests/ASTMatchers/Dynamic/VariantValueTest.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CXXOperatorCallExprTraverser.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksBinaryOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksCompoundAssignOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CallbacksUnaryOperator.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/InitListExprPostOrderNoQueue.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/InitListExprPreOrderNoQueue.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/TemplateArgumentLocTraverser.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M clang/www/cxx_status.html
M clang/www/make_cxx_dr_status
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
M flang/include/flang/Evaluate/traverse.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/runtime/complex-powi.cpp
A flang/test/Lower/Intrinsics/pow_complex16i.f90
A flang/test/Lower/Intrinsics/pow_complex16k.f90
M flang/test/Semantics/forall01.f90
M flang/test/Semantics/selecttype03.f90
M libc/docs/full_cross_build.rst
A libc/docs/gpu/building.rst
M libc/docs/gpu/index.rst
M libc/docs/gpu/rpc.rst
M libc/docs/gpu/using.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/docs/Status/SpaceshipPapers.csv
M libcxx/include/span
M libcxx/utils/ci/docker-compose.yml
M lld/ELF/ScriptParser.cpp
M lld/test/ELF/lto/amdgcn-oses.ll
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenACC/ACC.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Support/Casting.h
M llvm/include/llvm/TableGen/DirectiveEmitter.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/MCA/Stages/InOrderIssueStage.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
A llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMCInstLower.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll
M llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
M llvm/test/Analysis/ScalarEvolution/add-like-or.ll
M llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll
M llvm/test/Analysis/ScalarEvolution/addrec-sub-nsw.ll
M llvm/test/Analysis/ScalarEvolution/alloca.ll
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll
M llvm/test/Analysis/ScalarEvolution/decrementing_addrecs.ll
M llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll
M llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-select.ll
M llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll
M llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll
M llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
M llvm/test/Analysis/ScalarEvolution/fold.ll
M llvm/test/Analysis/ScalarEvolution/huge-trip-multiple.ll
M llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
M llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll
M llvm/test/Analysis/ScalarEvolution/invalidation.ll
M llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll
M llvm/test/Analysis/ScalarEvolution/load.ll
M llvm/test/Analysis/ScalarEvolution/logical-operations.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll
M llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll
M llvm/test/Analysis/ScalarEvolution/max-expr-cache.ll
M llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll
M llvm/test/Analysis/ScalarEvolution/max-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll
M llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
M llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
M llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
M llvm/test/Analysis/ScalarEvolution/nsw-offset.ll
M llvm/test/Analysis/ScalarEvolution/nsw.ll
M llvm/test/Analysis/ScalarEvolution/outer_phi.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll
M llvm/test/Analysis/ScalarEvolution/pr25369.ll
M llvm/test/Analysis/ScalarEvolution/pr34538.ll
M llvm/test/Analysis/ScalarEvolution/pr48225.ll
M llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll
M llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
M llvm/test/Analysis/ScalarEvolution/range-signedness.ll
M llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll
M llvm/test/Analysis/ScalarEvolution/ranges.ll
M llvm/test/Analysis/ScalarEvolution/sdiv.ll
M llvm/test/Analysis/ScalarEvolution/sext-add-inreg-loop.ll
M llvm/test/Analysis/ScalarEvolution/sext-mul.ll
M llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll
M llvm/test/Analysis/ScalarEvolution/shift-op.ll
M llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
M llvm/test/Analysis/ScalarEvolution/sle.ll
M llvm/test/Analysis/ScalarEvolution/smax-br-phi-idioms.ll
M llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll
M llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll
M llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll
M llvm/test/Analysis/ScalarEvolution/srem.ll
M llvm/test/Analysis/ScalarEvolution/symbolic_max_exit_count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-minmax.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
M llvm/test/Analysis/ScalarEvolution/trip-count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count10.ll
M llvm/test/Analysis/ScalarEvolution/trip-count12.ll
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
M llvm/test/Analysis/ScalarEvolution/trip-count14.ll
M llvm/test/Analysis/ScalarEvolution/trip-count15.ll
M llvm/test/Analysis/ScalarEvolution/trip-count2.ll
M llvm/test/Analysis/ScalarEvolution/trip-count3.ll
M llvm/test/Analysis/ScalarEvolution/trip-count4.ll
M llvm/test/Analysis/ScalarEvolution/trip-count6.ll
M llvm/test/Analysis/ScalarEvolution/trip-count7.ll
M llvm/test/Analysis/ScalarEvolution/trip-count8.ll
M llvm/test/Analysis/ScalarEvolution/trip-count9.ll
M llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/trip-multiple.ll
M llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll
M llvm/test/Analysis/ScalarEvolution/unknown_phis.ll
M llvm/test/Analysis/ScalarEvolution/widenable-condition.ll
M llvm/test/Bitcode/upgrade-module-flag.ll
A llvm/test/CodeGen/AArch64/ldp-stp-unknown-size.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
A llvm/test/CodeGen/AMDGPU/fpenv.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-func.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-asan.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
A llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
A llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
M llvm/test/CodeGen/X86/psadbw.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/MC/AMDGPU/bf16_imm.s
M llvm/test/MC/AMDGPU/gfx1150_asm_features.s
M llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
M llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_exp.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_global_load_tr.s
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mtbuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mtbuf_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vdsdir.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd_errs.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopd_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vsample.s
M llvm/test/MC/AMDGPU/gfx12_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx12_asm_wmma_w64.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_salu_float.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_global_load_tr.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mtbuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vdsdir.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vinterp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_err.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopd_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w32.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w64.txt
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/phi-select-constant.ll
M llvm/test/Transforms/InstCombine/pr63791.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/sink_to_unreachable.ll
M llvm/test/Transforms/InstCombine/unreachable-code.ll
M llvm/test/Transforms/LoopDeletion/invalidate-scev-after-hoisting.ll
M llvm/test/Transforms/LoopSimplify/preserve-scev.ll
A llvm/test/tools/llvm-mca/AMDGPU/carried-over.s
M llvm/test/tools/llvm-reduce/reduce-module-flags.ll
M llvm/unittests/Support/Casting.cpp
M llvm/utils/TableGen/DirectiveEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M mlir/CMakeLists.txt
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/IR/BuiltinAttributeInterfaces.h
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/mlir-tblgen/rewriter-errors.td
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M openmp/tools/archer/ompt-tsan.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
add missing "add" in a comment.
Created using spr 1.3.5-bogner
Compare: https://github.com/llvm/llvm-project/compare/5aca4c05b840...f31fc0ba494a
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list