[all-commits] [llvm/llvm-project] f7d354: [Hexagon] Fix shift value when folding shl DAG nod...

[yandalur via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7d354af5714358d7ad83e58a1016c3f385416dd
      https://github.com/llvm/llvm-project/commit/f7d354af5714358d7ad83e58a1016c3f385416dd
  Author: yandalur <quic_yandalur at quicinc.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    A llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll

  Log Message:
  -----------
  [Hexagon] Fix shift value when folding shl DAG node (#83853)

When folding (or (shl xx, s), (zext y)) to (COMBINE (shl xx, s-32), y),
fix resulting shift value in HexagonISD::COMBINE node to not generate
negative values.

---------

Co-authored-by: Yashas Andaluri <yandalur at qti.qualcomm.com>



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