[all-commits] [llvm/llvm-project] a770aa: Rename

[Wang Pengcheng via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscvnfc-add-helpers-for-rvv-register-classes
  Home:   https://github.com/llvm/llvm-project
  Commit: a770aac59b3f29ed3134bd5a3624d52c34c77e09
      https://github.com/llvm/llvm-project/commit/a770aac59b3f29ed3134bd5a3624d52c34c77e09
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

  Log Message:
  -----------
  Rename

Created using spr 1.3.4



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