[all-commits] [llvm/llvm-project] bec7ad: [RISCV] Add tests for vw{add, sub, mul} with nested ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bec7ad9fd6bceb6521448b24faddb01bc52de3a7
      https://github.com/llvm/llvm-project/commit/bec7ad9fd6bceb6521448b24faddb01bc52de3a7
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add tests for vw{add,sub,mul} with nested extend. NFC

These test cases show (op (ext a), (ext b)) patterns where the dest EEW is
more than 2 * source EEW. These could be lowered into widening ops where we
still have extend the operands, but at a smaller EEW.



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