[all-commits] [llvm/llvm-project] 228c73: [RISCV] Add tests for vsetvli/vsetvlimax with diff...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 228c737b3c2fdc22a431b65df3b9ec528db5e67f
      https://github.com/llvm/llvm-project/commit/228c737b3c2fdc22a431b65df3b9ec528db5e67f
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll
    A llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-knownbits.ll

  Log Message:
  -----------
  [RISCV] Add tests for vsetvli/vsetvlimax with different SEW/LMUL



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