[all-commits] [llvm/llvm-project] 341d67: [LLVM][AArch64][CodeGen] Mark FFR as a reserved re...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 341d674b6f1863d027ed30c44a14cd32599eb42d
      https://github.com/llvm/llvm-project/commit/341d674b6f1863d027ed30c44a14cd32599eb42d
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2024-03-05 (Tue, 05 Mar 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ffr-manipulation.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
    M llvm/test/CodeGen/AArch64/sve-ldnf1.mir
    M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
    M llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s

  Log Message:
  -----------
  [LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437)

This allows the removal of FFR related psuedo nodes that only existed to
work round machine verifier failures.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications