[all-commits] [llvm/llvm-project] 2c5d01: Revert "[SelectionDAG] Add `STRICT_BF16_TO_FP` and...
Mingming Liu via All-commits
all-commits at lists.llvm.org
Mon Mar 4 00:53:46 PST 2024
Branch: refs/heads/users/minglotus-6/spr/profile-refactor
Home: https://github.com/llvm/llvm-project
Commit: 2c5d01c2cfa80fd734b94833bdf7b5b3f6f2ebb0
https://github.com/llvm/llvm-project/commit/2c5d01c2cfa80fd734b94833bdf7b5b3f6f2ebb0
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
R compiler-rt/lib/builtins/extendbfsf2.c
M compiler-rt/lib/builtins/fp_extend.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
R llvm/test/CodeGen/X86/bfloat-constrained.ll
Log Message:
-----------
Revert "[SelectionDAG] Add `STRICT_BF16_TO_FP` and `STRICT_FP_TO_BF16` (#80056)"
This reverts commit b0c158bd947c360a4652eb0de3a4794f46deb88b.
The changes in `compiler-rt` broke tests.
Commit: 8300f30a9234ee46b2b941e8b07cb7d104c846cb
https://github.com/llvm/llvm-project/commit/8300f30a9234ee46b2b941e8b07cb7d104c846cb
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendbfsf2.c
M compiler-rt/lib/builtins/fp_extend.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/bfloat-constrained.ll
Log Message:
-----------
[SelectionDAG] Add `STRICT_BF16_TO_FP` and `STRICT_FP_TO_BF16` (#80056)
This patch adds the support for `STRICT_BF16_TO_FP` and
`STRICT_FP_TO_BF16`.
Commit: aa6ebf9be124664945f32f2be1167e6453788f40
https://github.com/llvm/llvm-project/commit/aa6ebf9be124664945f32f2be1167e6453788f40
Author: Daniel Martinez <danielpedromartinez at duck.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M openmp/libomptarget/include/Shared/SourceInfo.h
M openmp/libomptarget/include/omptarget.h
M openmp/libomptarget/plugins-nextgen/common/include/RPC.h
Log Message:
-----------
Replace some C headers with C++ ones (#82697)
#81434
Replaced some C headers with C++ ones
Co-authored-by: Daniel Martinez <danielmartinez at cock.li>
Commit: 23bc5b6392c61980d24cc23a61a020f7aaf858bf
https://github.com/llvm/llvm-project/commit/23bc5b6392c61980d24cc23a61a020f7aaf858bf
Author: David Majnemer <david.majnemer at gmail.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Mark bf16 as custom for truncating stores & add a comment
While we don't use SVE2 as a fallback for missing NEON instructions for
BF16, it is confusing to break symmetry with fp16.
While we are here, add a comment explaining how BF16 immediates work.
Commit: 43222bd3091db5403e3320d23a241a534c1eefec
https://github.com/llvm/llvm-project/commit/43222bd3091db5403e3320d23a241a534c1eefec
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-03-03 (Sun, 03 Mar 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
M llvm/test/CodeGen/SPIRV/half_no_extension.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
M llvm/test/CodeGen/SPIRV/opaque_pointers.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll
R llvm/test/CodeGen/SPIRV/opencl/metadata/kernel_arg_type_function_metadata.ll
R llvm/test/CodeGen/SPIRV/opencl/metadata/kernel_arg_type_module_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/vload2.ll
A llvm/test/CodeGen/SPIRV/opencl/vstore2.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
A llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
A llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
A llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
R llvm/test/CodeGen/SPIRV/pointers/two-bitcast-users.ll
M llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_legacy.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
Log Message:
-----------
[SPIR-V] Do not use OpenCL metadata for ptr element type resolution (#82678)
This pull request aims to remove any dependency on OpenCL/SPIR-V type
information in LLVM IR metadata. While, using metadata might simplify
and prettify the resulting SPIR-V output (and restore some of the
information missed in the transformation to opaque pointers), the
overall methodology for resolving kernel parameter types is highly
inefficient.
The high-level strategy is to assign kernel parameter types in this order:
1. Resolving the types using builtin function calls as mangled names
must contain type information or by looking up builtin definition in
SPIRVBuiltins.td. Then:
- Assigning the type temporarily using an intrinsic and later setting
the right SPIR-V type in SPIRVGlobalRegistry after IRTranslation
- Inserting a bitcast
2. Defaulting to LLVM IR types (in case of pointers the generic i8*
type or types from byval/byref attributes)
In case of type incompatibility (e.g. parameter defined initially as
sampler_t and later used as image_t) the error will be found early on
before IRTranslation (in the SPIRVEmitIntrinsics pass).
Commit: 354deba10a99136a3204dfa8128e53cd6e9558a7
https://github.com/llvm/llvm-project/commit/354deba10a99136a3204dfa8128e53cd6e9558a7
Author: Matthias Springer <me at m-sp.org>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/MemoryAllocation.cpp
Log Message:
-----------
[flang] Fix use-after-free in `MemoryAllocation.cpp` (#83768)
`AllocaOpConversion` takes an `ArrayRef<Operation *>`, but the
underlying `SmallVector<Operation *>` was dead by the time the pattern
ran.
Commit: a282109411596ef814aefeec735a2965d6aa4573
https://github.com/llvm/llvm-project/commit/a282109411596ef814aefeec735a2965d6aa4573
Author: Matthias Springer <me at m-sp.org>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][Transforms] Encapsulate dialect conversion options in `ConversionConfig` (#83754)
This commit adds a new `ConversionConfig` struct that allows users to
customize the dialect conversion. This configuration is similar to
`GreedyRewriteConfig` for the greedy pattern rewrite driver.
A few existing options are moved to this objects, simplifying the
dialect conversion API.
This is a re-upload of #82250. The Windows build breakage was fixed in #83768.
This reverts commit 60fbd6050107875956960c3ce35cf94b202d8675.
Commit: 3a146d5720fb9857cebc17fbc2d42fb589647680
https://github.com/llvm/llvm-project/commit/3a146d5720fb9857cebc17fbc2d42fb589647680
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
A llvm/test/tools/llvm-mca/AMDGPU/gfx940-mfma.s
Log Message:
-----------
AMDGPU: Partially re-add scheduling test for gfx940
31295bbe83c3ea9d8a3372efe34342a299d1018a reverted the original patch.
Submit part of the test that happens to not hit the sanitizer error,
which covers the instructions I more need test coverage for.
Commit: 8715f256911786520bb727ce067098d7082ac45c
https://github.com/llvm/llvm-project/commit/8715f256911786520bb727ce067098d7082ac45c
Author: Exile <2094247798 at qq.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CheckerDocumentation.cpp
Log Message:
-----------
[clang][StaticAnalyzer] fix function evalCall() typo in CheckerDocumentation (#83677)
```bool evalCall(const CallEvent &Call, CheckerContext &C)``` is corret form.
Co-authored-by: miaozhiyuan <miaozhiyuan at feysh.com>
Commit: 63725ab1196ac50509ad382fc12c56f6d8b5d874
https://github.com/llvm/llvm-project/commit/63725ab1196ac50509ad382fc12c56f6d8b5d874
Author: Luke Lau <luke at igalia.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/pr83017.ll
Log Message:
-----------
[RISCV] Add test for aliasing miscompile fixed by #83017. NFC
Previously we incorrectly removed the scalar load store pair here assuming it
was dead, when it actually aliased with the memset. This showed up as a
miscompile on SPEC CPU 2017 when compiling with -mrvv-vector-bits, and was only
triggered by the changes in #75531. This was fixed in #83017, but this patch
adds a test case for this specific miscompile.
For reference, the incorrect codegen was:
vsetvli a1, zero, e8, m4, ta, ma
vmv.v.i v8, 0
vs4r.v v8, (a0)
addi a1, a0, 80
vsetivli zero, 16, e8, m1, ta, ma
vmv.v.i v8, 0
vs1r.v v8, (a1)
addi a0, a0, 64
vs1r.v v8, (a0)
Commit: c7fdd8c11e54585dc9d15d63de9742067e0506b9
https://github.com/llvm/llvm-project/commit/c7fdd8c11e54585dc9d15d63de9742067e0506b9
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M llvm/include/llvm/ADT/GenericConvergenceVerifier.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
A llvm/include/llvm/CodeGen/MachineConvergenceVerifier.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/ValueTypes.cpp
M llvm/lib/IR/ConvergenceVerifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
Log Message:
-----------
Restore "Implement convergence control in MIR using SelectionDAG (#71785)"
Original commit 79889734b940356ab3381423c93ae06f22e772c9.
Perviously reverted in commit a2afcd5721869d1d03c8146bae3885b3385ba15e.
LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:
1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
control intrinsics.
2. Model token values as untyped virtual registers in MIR.
The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.
The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.
Commit: 3d14e85578ab4f91bfe74497c69ad5dec3007621
https://github.com/llvm/llvm-project/commit/3d14e85578ab4f91bfe74497c69ad5dec3007621
Author: Ben Shi <2283975856 at qq.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.td
Log Message:
-----------
[AVR][NFC] Reformat target description files (#83755)
Commit: a015f591766e4e3a3a23bbab7ca5dfec8f8deb18
https://github.com/llvm/llvm-project/commit/a015f591766e4e3a3a23bbab7ca5dfec8f8deb18
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M flang/test/Fir/memory-allocation-opt.fir
Log Message:
-----------
[flang] disable memory-allocation-opt.fir test on windows (#83535)
It is randomly failing in windows pre-merge checks and causing noise in
Github PRs.
Not clear why it is crashing on windows, issue opened:
https://github.com/llvm/llvm-project/issues/83534
Commit: 408d4e131ef7b30c3bc419f5219f7ca20ca9ac1d
https://github.com/llvm/llvm-project/commit/408d4e131ef7b30c3bc419f5219f7ca20ca9ac1d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M flang/include/flang/Optimizer/CodeGen/CodeGen.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
Log Message:
-----------
[flang][NFC] Expose FIR to LLVM patterns (#83492)
The FIR dialect has been initiated before many interfaces have been
introduced to MLIR. This patch expose the FIR to LLVM patterns in a
`populateFIRToLLVMConversionPatterns` function. The idea is to be able
to add the `ConvertToLLVMPatternInterface`. This is not directly
possible since the FIR dialect does not currently use the table
infrastructure for its definition.
Follow up patches will move the FIR dialect definition to table gen and
then implement the interface.
Commit: 96b2c3bde72ec6b681b03370f9650cfd03e66753
https://github.com/llvm/llvm-project/commit/96b2c3bde72ec6b681b03370f9650cfd03e66753
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
A llvm/test/MC/X86/apx/long-instruction-err.s
Log Message:
-----------
[X86][MC] Report error when the instruction length exceeds 15 bytes (#83708)
The instruction-size limit of 15 bytes still applies to APX
instructions.
Note that it is possible for an EVEX-encoded legacy instruction to reach
the 15-byte instruction length limit: 4
bytes of EVEX prefix + 1 byte of opcode + 1 byte of ModRM + 1 byte of
SIB + 4 bytes of displacement + 4 bytes of immediate = 15 bytes in
total, e.g.
```
addq $184, -96, %rax # encoding:
[0x62,0xf4,0xfc,0x18,0x81,0x04,0x25,0xa0,0xff,0xff,0xff,0xb8,0x00,0x00,0x00]
```
If we added a segment prefix like fs, the length would be 16.
In such a case, no additional (ASIZE or segment override) prefix can be
used.
To help users find this issue earlier, especially for assembler users,
we change
the internal compiler error to error in this patch.
Diagnostic is aligned with GAS
https://sourceware.org/bugzilla/show_bug.cgi?id=31323
Commit: 7af4e8bcc354d2bd7e46ecf547172b1f19ddde3e
https://github.com/llvm/llvm-project/commit/7af4e8bcc354d2bd7e46ecf547172b1f19ddde3e
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/analyzer-config.c
Log Message:
-----------
[clang][analyzer] Change default value of checker option in unix.StdCLibraryFunctions. (#80457)
Default value of checker option `ModelPOSIX` is changed to `true`.
Documentation is updated.
Commit: db76af28f600a2607152096cf623560705f0215f
https://github.com/llvm/llvm-project/commit/db76af28f600a2607152096cf623560705f0215f
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M mlir/lib/Query/Query.cpp
Log Message:
-----------
[mlir-query] Fix ambiguous overload
gcc7 fix didn't work (but unfortunately didn't get a notification and
forgot to check), this should hopefully address the ambiguous overload.
I can't repro locally/trying to create docker image for testing.
Commit: 0f18694d8cb3136e3a813aa13111d4a324100be6
https://github.com/llvm/llvm-project/commit/0f18694d8cb3136e3a813aa13111d4a324100be6
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-03-04 (Mon, 04 Mar 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CheckerDocumentation.cpp
M clang/test/Analysis/analyzer-config.c
M compiler-rt/lib/builtins/extendbfsf2.c
M compiler-rt/lib/builtins/fp_extend.h
M flang/include/flang/Optimizer/CodeGen/CodeGen.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/MemoryAllocation.cpp
M flang/test/Fir/memory-allocation-opt.fir
M llvm/include/llvm/ADT/GenericConvergenceVerifier.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
A llvm/include/llvm/CodeGen/MachineConvergenceVerifier.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/ValueTypes.cpp
M llvm/lib/IR/ConvergenceVerifier.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
A llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
A llvm/test/CodeGen/RISCV/rvv/pr83017.ll
M llvm/test/CodeGen/SPIRV/function/alloca-load-store.ll
M llvm/test/CodeGen/SPIRV/half_no_extension.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-nested-composite-store.ll
M llvm/test/CodeGen/SPIRV/instructions/undef-simple-composite-store.ll
M llvm/test/CodeGen/SPIRV/opaque_pointers.ll
M llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll
R llvm/test/CodeGen/SPIRV/opencl/metadata/kernel_arg_type_function_metadata.ll
R llvm/test/CodeGen/SPIRV/opencl/metadata/kernel_arg_type_module_metadata.ll
M llvm/test/CodeGen/SPIRV/opencl/vload2.ll
A llvm/test/CodeGen/SPIRV/opencl/vstore2.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll
M llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll
A llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll
A llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll
A llvm/test/CodeGen/SPIRV/pointers/store-operand-ptr-to-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/two-bitcast-or-param-users.ll
R llvm/test/CodeGen/SPIRV/pointers/two-bitcast-users.ll
M llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_legacy.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
A llvm/test/MC/X86/apx/long-instruction-err.s
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/lit.local.cfg
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
A llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
A llvm/test/tools/llvm-mca/AMDGPU/gfx940-mfma.s
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Query/Query.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M openmp/libomptarget/include/Shared/SourceInfo.h
M openmp/libomptarget/include/omptarget.h
M openmp/libomptarget/plugins-nextgen/common/include/RPC.h
Log Message:
-----------
Merge branch 'main' into users/minglotus-6/spr/profile-refactor
Compare: https://github.com/llvm/llvm-project/compare/919f9a2f291f...0f18694d8cb3
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