[all-commits] [llvm/llvm-project] 63725a: [RISCV] Add test for aliasing miscompile fixed by ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 63725ab1196ac50509ad382fc12c56f6d8b5d874
      https://github.com/llvm/llvm-project/commit/63725ab1196ac50509ad382fc12c56f6d8b5d874
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-04 (Mon, 04 Mar 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/pr83017.ll

  Log Message:
  -----------
  [RISCV] Add test for aliasing miscompile fixed by #83017. NFC

Previously we incorrectly removed the scalar load store pair here assuming it
was dead, when it actually aliased with the memset.  This showed up as a
miscompile on SPEC CPU 2017 when compiling with -mrvv-vector-bits, and was only
triggered by the changes in #75531.  This was fixed in #83017, but this patch
adds a test case for this specific miscompile.

For reference, the incorrect codegen was:

	vsetvli	a1, zero, e8, m4, ta, ma
	vmv.v.i	v8, 0
	vs4r.v	v8, (a0)
	addi	a1, a0, 80
	vsetivli	zero, 16, e8, m1, ta, ma
	vmv.v.i	v8, 0
	vs1r.v	v8, (a1)
	addi	a0, a0, 64
	vs1r.v	v8, (a0)



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