[all-commits] [llvm/llvm-project] 756166: [AMDGPU] Improve detection of non-null addrspaceca...

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 756166e342a3692fd8de1ad1c5620df516bac33a
      https://github.com/llvm/llvm-project/commit/756166e342a3692fd8de1ad1c5620df516bac33a
  Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
  Date:   2024-03-01 (Fri, 01 Mar 2024)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    A llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null-vector.ll
    A llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll

  Log Message:
  -----------
  [AMDGPU] Improve detection of non-null addrspacecast operands (#82311)

Use IR analysis to infer when an addrspacecast operand is nonnull, then
lower it to an intrinsic that the DAG can use to skip the null check.

I did this using an intrinsic as it's non-intrusive. An alternative
would have been to allow something like `!nonnull` on `addrspacecast`
then lower that to a custom opcode (or add an operand to the
addrspacecast MIR/DAG opcodes), but it's a lot of boilerplate for just
one target's use case IMO.

I'm hoping that when we switch to GISel that we can move all this logic
to the MIR level without losing info, but currently the DAG doesn't see
enough so we need to act in CGP.

Fixes: SWDEV-316445



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications