[all-commits] [llvm/llvm-project] d1924f: [PowerPC] Do not generate `isel` instruction if ta...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Mar 1 04:38:22 PST 2024
Branch: refs/heads/users/alexey-bataev/spr/slpfiximprove-potential-masked-gather-loads-analysis
Home: https://github.com/llvm/llvm-project
Commit: d1924f0474b65fe3189ffd658a12f452e4696c28
https://github.com/llvm/llvm-project/commit/d1924f0474b65fe3189ffd658a12f452e4696c28
Author: Kai Luo <lkail at cn.ibm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
M llvm/test/CodeGen/PowerPC/expand-isel-to-branch.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
M llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
M llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
M llvm/test/CodeGen/PowerPC/funnel-shift.ll
M llvm/test/CodeGen/PowerPC/i1-to-double.ll
M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/pr43976.ll
M llvm/test/CodeGen/PowerPC/pr49509.ll
M llvm/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll
M llvm/test/CodeGen/PowerPC/select-cc-no-isel.ll
M llvm/test/CodeGen/PowerPC/select.ll
M llvm/test/CodeGen/PowerPC/select_const.ll
M llvm/test/CodeGen/PowerPC/smulfixsat.ll
M llvm/test/CodeGen/PowerPC/spe.ll
M llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/PowerPC/umulfixsat.ll
M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/PowerPC/varargs.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
Log Message:
-----------
[PowerPC] Do not generate `isel` instruction if target doesn't have this instruction (#72845)
When expand `select_cc` in finalize-isel, we should not generate `isel`
for targets not feature it.
Commit: 7d7d4752a8f3d7b83586c10a882f974d821c0c53
https://github.com/llvm/llvm-project/commit/7d7d4752a8f3d7b83586c10a882f974d821c0c53
Author: ZijunZhaoCCK <88353225+ZijunZhaoCCK at users.noreply.github.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Set feature test macros __cpp_lib_ranges_contains and__cpp_lib_ranges_starts_ends_with (#81816)
ranges::contains: fdd089b50063
ranges::starts_with: 205175578e0d
ranges::ends_with: 0218ea4aaa54
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 5b058709536dd883980722ee000bb7b8c7b2cd8b
https://github.com/llvm/llvm-project/commit/5b058709536dd883980722ee000bb7b8c7b2cd8b
Author: Felix (Ting Wang) <Ting.Wang.SH at ibm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/CodeGen/PowerPC/aix-tls-model.cpp
M clang/test/Sema/aix-attr-tls_model.c
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/XCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
A llvm/test/CodeGen/PowerPC/aix-tls-ld-xcoff-reloc-large.ll
A llvm/test/CodeGen/PowerPC/aix-tls-local-dynamic.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
Log Message:
-----------
[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)
Supports TLS local-dynamic on AIX, generates below sequence of code:
```
.tc foo[TC],foo[TL]@ld # Variable offset, ld relocation specifier
.tc mh[TC],mh[TC]@ml # Module handle for the caller
lwz 3,mh[TC]\(2\) $$ For 64-bit: ld 3,mh[TC]\(2\)
bla .__tls_get_mod # Modifies r0,r3,r4,r5,r11,lr,cr0
#r3 = &TLS for module
lwz 4,foo[TC]\(2\) $$ For 64-bit: ld 4,foo[TC]\(2\)
add 5,3,4 # Compute &foo
.rename mh[TC], "\_$TLSML" # Symbol for the module handle must have the name "_$TLSML"
```
---------
Co-authored-by: tingwang <tingwang at tingwangs-MBP.lan>
Co-authored-by: tingwang <tingwang at tingwangs-MacBook-Pro.local>
Commit: 5899599b01d86545896bd21bd15fb5cb619bd6c7
https://github.com/llvm/llvm-project/commit/5899599b01d86545896bd21bd15fb5cb619bd6c7
Author: Yinying Li <107574043+yinying-lisa-li at users.noreply.github.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir
Log Message:
-----------
[mlir][sparse] Migration to sparse_tensor.print (#83506)
Continuous efforts #83357. Previously reverted #83377.
Commit: 9a12b0a60084b2b92f728e1bddec884a47458459
https://github.com/llvm/llvm-project/commit/9a12b0a60084b2b92f728e1bddec884a47458459
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M lldb/include/lldb/API/SBProcess.h
M lldb/include/lldb/Utility/AddressableBits.h
M lldb/include/lldb/lldb-defines.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/AddressableBits.cpp
A lldb/test/API/python_api/process/address-masks/Makefile
A lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
A lldb/test/API/python_api/process/address-masks/main.c
Log Message:
-----------
[lldb] Add SBProcess methods for get/set/use address masks (#83095)
I'm reviving a patch from phabracator, https://reviews.llvm.org/D155905
which was approved but I wasn't thrilled with all the API I was adding
to SBProcess for all of the address mask types / memory regions. In this
update, I added enums to control type address mask type (code, data,
any) and address space specifiers (low, high, all) with defaulted
arguments for the most common case.
This patch is also fixing a bug in the "addressable bits to address
mask" calculation I added in AddressableBits::SetProcessMasks. If lldb
were told that 64 bits are valid for addressing, this method would
overflow the calculation and set an invalid mask. Added tests to check
this specific bug while I was adding these APIs.
rdar://123530562
Commit: 7ceb74f5b74fa4a0b68ad911afd3cad945f640a3
https://github.com/llvm/llvm-project/commit/7ceb74f5b74fa4a0b68ad911afd3cad945f640a3
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_procmaps_bsd.cpp
Log Message:
-----------
[compiler-rt] fix BSD procmaps stack frame size limit warning. (#82887)
Commit: e8ce864a36ba02ddb63877905d49f1e9ac60b544
https://github.com/llvm/llvm-project/commit/e8ce864a36ba02ddb63877905d49f1e9ac60b544
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M lldb/include/lldb/API/SBProcess.h
M lldb/include/lldb/Utility/AddressableBits.h
M lldb/include/lldb/lldb-defines.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/AddressableBits.cpp
R lldb/test/API/python_api/process/address-masks/Makefile
R lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
R lldb/test/API/python_api/process/address-masks/main.c
Log Message:
-----------
Revert "[lldb] Add SBProcess methods for get/set/use address masks (#83095)"
This reverts commit 9a12b0a60084b2b92f728e1bddec884a47458459.
TestAddressMasks fails its first test on lldb-x86_64-debian,
lldb-arm-ubuntu, lldb-aarch64-ubuntu bots. Reverting while
investigating.
Commit: e7c3cd245665042bbae163f7280aceed35f0fee5
https://github.com/llvm/llvm-project/commit/e7c3cd245665042bbae163f7280aceed35f0fee5
Author: Kirill Stoimenov <87100199+kstoimenov at users.noreply.github.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
A llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out-no-ps.ll
A llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
Log Message:
-----------
[HWASAN] Implement selective instrumentation based on profiling information (#83503)
Commit: 2cdf611c02392112860e661e8251efa8b1335cc2
https://github.com/llvm/llvm-project/commit/2cdf611c02392112860e661e8251efa8b1335cc2
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
[compiler-rt][Fuzzer] SetThreadName windows implementation new try. (#76761)
SetThreadDescription symbol needs to be dynamically loaded before usage.
Then using a wide string buffer, since we re using a null terminated
string, we can use MultiByteToWideChar -1 as 4th argument to finally set
the thread name.
Previously `SetThreadDescription` was called directly causing crash.
It was reverted in dd3aa26fc8e9de37a39611f7a6a602bcb4153784
Commit: cf68c0427d9d3816eefcfe7d3d648a98146c07cf
https://github.com/llvm/llvm-project/commit/cf68c0427d9d3816eefcfe7d3d648a98146c07cf
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M libc/include/llvm-libc-macros/float-macros.h
Log Message:
-----------
[libc] Ignore -Winclude-next-absolute-path warning in float-macros.h (#83513)
Commit: 5b6e58c565cf809e4133a10ff9d9b096754bea1e
https://github.com/llvm/llvm-project/commit/5b6e58c565cf809e4133a10ff9d9b096754bea1e
Author: Alexander M <iammorjj at gmail.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M lldb/test/API/lang/c/local_variables/TestLocalVariables.py
Log Message:
-----------
Revert "XFAIL TestLocalVariables.py on Windows" (#83454)
This reverts commit 3434472ed74141848634b5eb3cd625d651e22562.
Closes #43097.
Commit: 39c24c52f641849a648e3b01310ed7c3f2c8d91b
https://github.com/llvm/llvm-project/commit/39c24c52f641849a648e3b01310ed7c3f2c8d91b
Author: jameshu15869 <55058507+jameshu15869 at users.noreply.github.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
Log Message:
-----------
[libc] Allow libc to build on Red Hat (#83517)
Currently, `libc` fails when building on redhat because the triple
format uses `redhat` instead of `linux` (The same problem as openSUSE).
This PR changes `libc` to accept `redhat` as a valid Linux triple.
---------
Co-authored-by: Joseph Huber <huberjn at outlook.com>
Commit: 8171f6d12eafbd4a67ad263770c142d51504d834
https://github.com/llvm/llvm-project/commit/8171f6d12eafbd4a67ad263770c142d51504d834
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M lldb/include/lldb/Core/Progress.h
Log Message:
-----------
[lldb][progress][NFC] Fix Doxygen information (#83502)
Commit: 2023a230d122d6971c5ff90615c128e7e711b08f
https://github.com/llvm/llvm-project/commit/2023a230d122d6971c5ff90615c128e7e711b08f
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
Log Message:
-----------
[RISCV] Move V0 to the end of register allocation order (#82967)
According to
https://riscv-optimization-guide-riseproject-c94355ae3e6872252baa952524.gitlab.io/riscv-optimization-guide.html:
> The v0 register defined by the RISC-V vector extension is special in
> that it can be used both as a general purpose vector register and also
> as a mask register. As a preference, use registers other than v0 for
> non-mask values. Otherwise data will have to be moved out of v0 when a
> mask is required in an operation. v0 may be used when all other
> registers are in use, and using v0 would avoid spilling register state
> to memory.
And using V0 register may stall masking pipeline and stop chaining
for some microarchitectures.
So we should try to not use V0 and register groups contained it as
much as possible. We achieve this via moving V0 to the end of RA
order.
Commit: 4551f53523074cd4e2f93a6f79313ca2cdcc40d2
https://github.com/llvm/llvm-project/commit/4551f53523074cd4e2f93a6f79313ca2cdcc40d2
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/RNBRemote.h
Log Message:
-----------
[lldb] [debugserver] fix qLaunchSuccess error, add QErrorStringInPacketSupported (#82593)
Pavel added an extension to lldb's gdb remote serial protocol that
allows the debug stub to append an error message (ascii hex encoded)
after an error response packet Exx. This was added in 2017 in
https://reviews.llvm.org/D34945 . lldb sends the
QErrorStringInPacketSupported packet and then the remote stub may add
these error strings.
debugserver has two bugs in its use of extended error messages: the
vAttach family would send the extended error string without checking if
the mode had been enabled. And qLaunchSuccess would not properly format
its error response packet (missing the hex digits, did not asciihex
encode the string).
There is also a bug in the HandlePacket_D (detach) packet where the
error packets did not include hex digits, but this one does not append
an error string.
I'm adding a new RNBRemote::SendErrorPacket() and routing all error
packet returns though this one method. It takes an optional second
string which is the longer error message; it now handles appending it to
the Exx response or not, depending on the QErrorStringInPacketSupported
state. I updated all packets to send their errors via this method.
Commit: 8fd011ecc61fa83b9520a971aba1fa651a011bff
https://github.com/llvm/llvm-project/commit/8fd011ecc61fa83b9520a971aba1fa651a011bff
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/RISCVTargetParser.cpp
Log Message:
-----------
[RISCV] Add getFeaturesForCPU function support (#83269)
This function parse the cpu and return it's supported
features placed in EnabledFeatures. It is same as the
one in X86TargetParser and also is used in IREE.
Commit: 8116dfb8b58a65e78e341f09f5728d345f086b7b
https://github.com/llvm/llvm-project/commit/8116dfb8b58a65e78e341f09f5728d345f086b7b
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M clang/lib/InstallAPI/Frontend.cpp
Log Message:
-----------
[InstallAPI] Use unique identifiers for input buffers (#83523)
Commit: 346766eae8cb8949c2c13b85c0d1e6ff4869a77e
https://github.com/llvm/llvm-project/commit/346766eae8cb8949c2c13b85c0d1e6ff4869a77e
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-29 (Thu, 29 Feb 2024)
Changed paths:
M llvm/include/llvm/TextAPI/Record.h
M llvm/lib/TextAPI/RecordVisitor.cpp
Log Message:
-----------
[TextAPI] Fixup symbol names of ivars from extensions (#83525)
Commit: edd0ef4f3cb0ebc4eadc7a207edb9c849e894fc3
https://github.com/llvm/llvm-project/commit/edd0ef4f3cb0ebc4eadc7a207edb9c849e894fc3
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/loop_align_count.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.mir
Log Message:
-----------
Add "REQUIRES: asserts" to 2 tests added in #83379 using "-debug-only" run arguments.
Commit: dca32a3b594b3c91f9766a9312b5d82534910fa1
https://github.com/llvm/llvm-project/commit/dca32a3b594b3c91f9766a9312b5d82534910fa1
Author: Matthias Gehre <matthias.gehre at amd.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/PDL/IR/PDLOps.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/lib/Conversion/PDLToPDLInterp/PDLToPDLInterp.cpp
M mlir/lib/Conversion/PDLToPDLInterp/Predicate.h
M mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp
M mlir/lib/Dialect/PDL/IR/PDL.cpp
M mlir/lib/Rewrite/ByteCode.cpp
M mlir/lib/Tools/PDLL/Parser/Parser.cpp
M mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir
A mlir/test/Conversion/PDLToPDLInterp/use-constraint-result.mlir
M mlir/test/Dialect/PDL/ops.mlir
M mlir/test/Rewrite/pdl-bytecode.mlir
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/lib/Rewrite/TestPDLByteCode.cpp
M mlir/test/mlir-pdll/Parser/constraint-failure.pdll
M mlir/test/mlir-pdll/Parser/constraint.pdll
M mlir/test/python/dialects/pdl_ops.py
Log Message:
-----------
[mlir][PDL] Add support for native constraints with results (#82760)
>From https://reviews.llvm.org/D153245
This adds support for native PDL (and PDLL) C++ constraints to return
results.
This is useful for situations where a pattern checks for certain
constraints of multiple interdependent attributes and computes a new
attribute value based on them. Currently, for such an example it is
required to escape to C++ during matching to perform the check and after
a successful match again escape to native C++ to perform the computation
during the rewriting part of the pattern. With this work we can do the
computation in C++ during matching and use the result in the rewriting
part of the pattern. Effectively this enables a choice in the trade-off
of memory consumption during matching vs recomputation of values.
This is an example of a situation where this is useful: We have two
operations with certain attributes that have interdependent constraints.
For instance `attr_foo: one_of [0, 2, 4, 8], attr_bar: one_of [0, 2, 4,
8]` and `attr_foo == attr_bar`. The pattern should only match if all
conditions are true. The new operation should be created with a new
attribute which is computed from the two matched attributes e.g.
`attr_baz = attr_foo * attr_bar`. For the check we already escape to
native C++ and have all values at hand so it makes sense to directly
compute the new attribute value as well:
```
Constraint checkAndCompute(attr0: Attr, attr1: Attr) -> Attr;
Pattern example with benefit(1) {
let foo = op<test.foo>() {attr = attr_foo : Attr};
let bar = op<test.bar>(foo) {attr = attr_bar : Attr};
let attr_baz = checkAndCompute(attr_foo, attr_bar);
rewrite bar with {
let baz = op<test.baz> {attr=attr_baz};
replace bar with baz;
};
}
```
To achieve this the following notable changes were necessary:
PDLL:
- Remove check in PDLL parser that prevented native constraints from
returning results
PDL:
- Change PDL definition of pdl.apply_native_constraint to allow variadic
results
PDL_interp:
- Change PDL_interp definition of pdl_interp.apply_constraint to allow
variadic results
PDLToPDLInterp Pass:
The input to the pass is an arbitrary number of PDL patterns. The pass
collects the predicates that are required to match all of the pdl
patterns and establishes an ordering that allows creation of a single
efficient matcher function to match all of them. Values that are matched
and possibly used in the rewriting part of a pattern are represented as
positions. This allows fusion and thus reusing a single position for
multiple matching patterns. Accordingly, we introduce
ConstraintPosition, which records the type and index of the result of
the constraint. The problem is for the corresponding value to be used in
the rewriting part of a pattern it has to be an input to the
pdl_interp.record_match operation, which is generated early during the
pass such that its surrounding block can be referred to by branching
operations. In consequence the value has to be materialized after the
original pdl.apply_native_constraint has been deleted but before we get
the chance to generate the corresponding pdl_interp.apply_constraint
operation. We solve this by emitting a placeholder value when a
ConstraintPosition is evaluated. These placeholder values (due to fusion
there may be multiple for one constraint result) are replaced later when
the actual pdl_interp.apply_constraint operation is created.
Changes since the phabricator review:
- Addressed all comments
- In particular, removed registerConstraintFunctionWithResults and
instead changed registerConstraintFunction so that contraint functions
always have results (empty by default)
- Thus we don't need to reuse `rewriteFunctions` to store constraint
functions with results anymore, and can instead use
`constraintFunctions`
- Perform a stable sort of ConstraintQuestion, so that
ConstraintQuestion appear before other ConstraintQuestion that use their
results.
- Don't create placeholders for pdl_interp::ApplyConstraintOp. Instead
generate the `pdl_interp::ApplyConstraintOp` before generating the
successor block.
- Fixed a test failure in the pdl python bindings
Original code by @martin-luecke
Co-authored-by: martin-luecke <martinpaul.luecke at amd.com>
Commit: c80e6edba4a9593f0587e27fa0ac825ebe174afd
https://github.com/llvm/llvm-project/commit/c80e6edba4a9593f0587e27fa0ac825ebe174afd
Author: Matthias Gehre <matthias.gehre at amd.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/PDL/IR/PDLOps.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/lib/Conversion/PDLToPDLInterp/PDLToPDLInterp.cpp
M mlir/lib/Conversion/PDLToPDLInterp/Predicate.h
M mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp
M mlir/lib/Dialect/PDL/IR/PDL.cpp
M mlir/lib/Rewrite/ByteCode.cpp
M mlir/lib/Tools/PDLL/Parser/Parser.cpp
M mlir/test/Conversion/PDLToPDLInterp/pdl-to-pdl-interp-matcher.mlir
R mlir/test/Conversion/PDLToPDLInterp/use-constraint-result.mlir
M mlir/test/Dialect/PDL/ops.mlir
M mlir/test/Rewrite/pdl-bytecode.mlir
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.cpp
M mlir/test/lib/Rewrite/TestPDLByteCode.cpp
M mlir/test/mlir-pdll/Parser/constraint-failure.pdll
M mlir/test/mlir-pdll/Parser/constraint.pdll
M mlir/test/python/dialects/pdl_ops.py
Log Message:
-----------
Revert "[mlir][PDL] Add support for native constraints with results (#82760)"
Due to buildbot failure https://lab.llvm.org/buildbot/#/builders/88/builds/72130
This reverts commit dca32a3b594b3c91f9766a9312b5d82534910fa1.
Commit: 012b697e7c3633ae17639b086414fd6c02127810
https://github.com/llvm/llvm-project/commit/012b697e7c3633ae17639b086414fd6c02127810
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/stream-note.c
Log Message:
-----------
[clang][analyzer] Add StreamChecker note tags for "indeterminate stream position". (#83288)
If a stream operation fails the position can become "indeterminate".
This may cause warning from the checker at a later operation. The new
note tag shows the place where the position becomes "indeterminate",
this is where a failure occurred.
Commit: 43bcedd1f09134478b7c8582bac86c78e2dbeb28
https://github.com/llvm/llvm-project/commit/43bcedd1f09134478b7c8582bac86c78e2dbeb28
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h
Log Message:
-----------
[compiler-rt] fix __sanitizer_siginfo type on freebsd. (#77379)
mostly interested in the first half of the type, adding also compile
time check.
Commit: 6c39fa9e9f198498ff7cf9646081437a0fc0882a
https://github.com/llvm/llvm-project/commit/6c39fa9e9f198498ff7cf9646081437a0fc0882a
Author: Dhruv Chawla (work) <dhruvc at nvidia.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/abs.ll
Log Message:
-----------
[AArch64][GlobalISel] Expand abs.v4i8 to v4i16 and abs.v2s16 to v2s32 (#81231)
GISel was currently falling back to SDAG for these functions, and this
matches the way SDAG currently generates code for these functions.
Commit: 420928b2fa8b00f23f0adcb19328014592455698
https://github.com/llvm/llvm-project/commit/420928b2fa8b00f23f0adcb19328014592455698
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/test/CodeGen/X86/apx/compress-evex.mir
Log Message:
-----------
[X86][CodeGen] Fix compile crash in EVEX compression for corner case
The base register of OPmi_ND may be allocated to the same physic
register as the ND operand.
OPmi_ND is not compressible b/c it has different semnatic from OPmi.
In this case, `isRedundantNewDataDest` should return false, otherwise
we would get error
Assertion `!IsNDLike && "Missing entry for ND-like instruction"' failed.
Commit: 128780b06f5bd0e586ee81e1e0e75f63c5664cfc
https://github.com/llvm/llvm-project/commit/128780b06f5bd0e586ee81e1e0e75f63c5664cfc
Author: martinboehme <mboehme at google.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TestingSupport.h
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Correctly treat empty initializer lists for unions. (#82986)
This fixes a crash introduced by
https://github.com/llvm/llvm-project/pull/82348
but also adds additional handling to make sure that we treat empty
initializer
lists for both unions and structs/classes correctly (see tests added in
this
patch).
Commit: 40c9a01773507e485f35aa76d3e31cf3ea8c3011
https://github.com/llvm/llvm-project/commit/40c9a01773507e485f35aa76d3e31cf3ea8c3011
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/lib/AST/Interp/Context.h
Log Message:
-----------
[clang][Interp][NFC] Add an assertion to classify(Expr*)
NFC but makes the backtrace easier to read in case the expression
somehow ends up being null.
Commit: ba8e9ace13c3c2dedf5c496455de822cba931862
https://github.com/llvm/llvm-project/commit/ba8e9ace13c3c2dedf5c496455de822cba931862
Author: Nick Anderson <nickleus27 at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
Log Message:
-----------
[AMDGPU] promote i1 arg type for amdgpu_cs (#82971)
fixes #68087
Not sure where to put regression tests for this pr? Also, should i1 args
not in reg also be promoted?
Commit: 4a5ec3cec8316234667897d99fa4ef1b1a132c43
https://github.com/llvm/llvm-project/commit/4a5ec3cec8316234667897d99fa4ef1b1a132c43
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AArch64/shufflevector.ll
Log Message:
-----------
Revert "[AArch64][GlobalISel] Legalize G_SHUFFLE_VECTOR for Odd-Sized Vectors" (#83544)
Reverts llvm/llvm-project#83038 due to failing build in Fuchsia build
https://lab.llvm.org/staging/#/builders/187/builds/1695
Commit: b051277d5ed8b22fce558272bf3bbbafb95245a5
https://github.com/llvm/llvm-project/commit/b051277d5ed8b22fce558272bf3bbbafb95245a5
Author: Pravin Jagtap <prjagtap at amd.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
Log Message:
-----------
Add llvm_v6i32_ty. NFC. (#83522)
Authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: e81ef463f10851bfbcd56a4f3450821f1e7c862f
https://github.com/llvm/llvm-project/commit/e81ef463f10851bfbcd56a4f3450821f1e7c862f
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
Log Message:
-----------
[FMV] Use lexicographic order of feature names when mangling. (#83464)
This decouples feature priorities from name mangling. Doing so will
prevent ABI breakages in case we change the feature priorities.
Formalized in ACLE here: https://github.com/ARM-software/acle/pull/303.
Commit: 990dbf2b7ebb1ddf1a53eb0b25061a0ea42f4ae1
https://github.com/llvm/llvm-project/commit/990dbf2b7ebb1ddf1a53eb0b25061a0ea42f4ae1
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
Log Message:
-----------
[clang][Interp] OpaqueValueExprs can have null subexprs
Commit: 062d78ef58ac26e1c6f82201151428d0b89cca21
https://github.com/llvm/llvm-project/commit/062d78ef58ac26e1c6f82201151428d0b89cca21
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
[compiler-rt][fuzzer] windows build unbreak proposal. (#83538)
shuffling the order of its includes.
Commit: 2a67c28abe8cfde47c5058abbeb4b5ff9a393192
https://github.com/llvm/llvm-project/commit/2a67c28abe8cfde47c5058abbeb4b5ff9a393192
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/include/llvm/IR/Module.h
Log Message:
-----------
[IR] Update getOrInsertFunction() docs for opaque pointers (NFC)
This can no longer return a bitcast, but the function type in
FunctionCallee may differ from the function type of the function.
Commit: 6ed67ca14cd05596a8253eeceb247d2743e00f6e
https://github.com/llvm/llvm-project/commit/6ed67ca14cd05596a8253eeceb247d2743e00f6e
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/lib/CodeGen/Targets/AArch64.cpp
Log Message:
-----------
[clang] Remove unused-lambda-capture in AArch64.cpp (NFC)
llvm-project/clang/lib/CodeGen/Targets/AArch64.cpp:886:26:
error: lambda capture 'TI' is not used [-Werror,-Wunused-lambda-capture]
886 | llvm::sort(Features, [&TI](const StringRef LHS, const StringRef RHS) {
| ~^~
1 error generated.
Commit: ec8df555702d85511290742388d28016b69468de
https://github.com/llvm/llvm-project/commit/ec8df555702d85511290742388d28016b69468de
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M lldb/test/CMakeLists.txt
Log Message:
-----------
[lldb][test][Windows] Don't check for pexpect with LLDB_ENFORCE_STRICT_TEST_REQUIREMENTS
See https://github.com/llvm/llvm-project/issues/22648 for why we don't use it on
Windows. Any pexpect tests are skipped there.
Commit: d50dec6f413ce1953bede94bdd11261b6684c7c4
https://github.com/llvm/llvm-project/commit/d50dec6f413ce1953bede94bdd11261b6684c7c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
Log Message:
-----------
Fix MSVC "not all control paths return a value" warnings. NFC.
Commit: 199bbe2b380b6fa4a23932739ae55f8890af459b
https://github.com/llvm/llvm-project/commit/199bbe2b380b6fa4a23932739ae55f8890af459b
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[MC] Teach checkAsmTiedOperandConstraints about optional operands (#81381)
At some point in the past, optional operands have become allowed in the
middle of an instruction. However, `checkAsmTiedOperandConstrains`
hasn't been modified to support this. This patch adds the support by
pulling operand offsets counting out of `convertToMCInst` and reusing it
in `checkAsmTiedOperandConstrains`.
Commit: 195744cca7fd7f1b33971e0f2cf07b8ae47f16b5
https://github.com/llvm/llvm-project/commit/195744cca7fd7f1b33971e0f2cf07b8ae47f16b5
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir
Log Message:
-----------
[mlir][VectorOps][nfc] Add result pretty printing to `vector.vscale` (#83439)
This will now print the value of `vector.vscale` as `%vscale` in IR
dumps which makes it easier to spot where things are scalable.
One test that depended on the value names has also been fixed.
Commit: 185b1df1b1f7bd88ff0159bc51d5ddaeca27106a
https://github.com/llvm/llvm-project/commit/185b1df1b1f7bd88ff0159bc51d5ddaeca27106a
Author: Pavel Iliin <Pavel.Iliin at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/aarch64-cpu-supports.c
M clang/test/Misc/warning-flags.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/builtin-cpu-supports.c
Log Message:
-----------
[X86][AArch64][PowerPC] __builtin_cpu_supports accepts unknown options. (#83515)
The patch fixes https://github.com/llvm/llvm-project/issues/83407
modifing __builtin_cpu_supports behaviour so that it returns false if
unsupported features names provided in parameter and issue a warning.
__builtin_cpu_supports is target independent, but currently supported by
X86, AArch64 and PowerPC only.
Commit: 4c8c335bcdb93e02b1bc08c5dbc7070af9bc91b5
https://github.com/llvm/llvm-project/commit/4c8c335bcdb93e02b1bc08c5dbc7070af9bc91b5
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
Log Message:
-----------
[AMDGPU] Rename hasGFX12Enc to hasRestrictedSOffset in BUF definitions. NFC. (#83434)
This just renames a tablegen argument to match the corresponding
subtarget feature.
Commit: 44c0bdb402271522a17704b4a18c8bf5efb55c4f
https://github.com/llvm/llvm-project/commit/44c0bdb402271522a17704b4a18c8bf5efb55c4f
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/test/HLFIR/all-lowering.fir
M flang/test/HLFIR/any-lowering.fir
M flang/test/HLFIR/count-lowering-default-int-kinds.fir
M flang/test/HLFIR/count-lowering.fir
M flang/test/HLFIR/dot_product-lowering.fir
M flang/test/HLFIR/extents-of-shape-of.f90
M flang/test/HLFIR/matmul-lowering.fir
M flang/test/HLFIR/maxloc-lowering.fir
M flang/test/HLFIR/maxval-lowering.fir
M flang/test/HLFIR/minloc-lowering.fir
M flang/test/HLFIR/minval-lowering.fir
M flang/test/HLFIR/mul_transpose.f90
M flang/test/HLFIR/product-lowering.fir
M flang/test/HLFIR/sum-lowering.fir
M flang/test/HLFIR/transpose-lowering.fir
M flang/test/Lower/convert.f90
Log Message:
-----------
[flang][HLFIR] Use GreedyPatternRewriter in LowerHLFIRIntrinsics (#83438)
In #83253 @matthias-springer pointed out that LowerHLFIRIntrinsics.cpp
should not be using rewrite patterns with the dialect conversion driver.
The intention of this pass is to lower HLFIR intrinsic operations into
FIR so it conceptually fits dialect conversion. However, dialect
conversion is much stricter about changing types when replacing
operations. This pass sometimes looses track of array bounds, resulting
in replacements with operations with different but compatible types
(expressions of the same rank and element types but with or without
compile time known array bounds). This is difficult to accommodate with
the dialect conversion driver and so I have changed to use the greedy
pattern rewriter.
There is a lot of test churn because the greedy pattern rewriter also
performs canonicalization.
Commit: 4c642b62b99fa128c180f28278637b32be5e5576
https://github.com/llvm/llvm-project/commit/4c642b62b99fa128c180f28278637b32be5e5576
Author: Martin Storsjö <martin at martin.st>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
Log Message:
-----------
[llvm-jitlink] [test] Add an XFAIL for a JITLink test on MinGW
This testcase fails on MinGW targets, because when compiling the
main() function, it gets an implicit call to __main(), which is
missing in this context.
Commit: d458a1931769aa4bcdb3fcd537c4ee946507ff1a
https://github.com/llvm/llvm-project/commit/d458a1931769aa4bcdb3fcd537c4ee946507ff1a
Author: David Green <david.green at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/aes.ll
M llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
Log Message:
-----------
[AArch64] Mark AESD and AESE instructions as commutative. (#83390)
This come from
https://discourse.llvm.org/t/combining-aes-and-xor-can-be-improved-further/77248.
These instructions start out with:
```
XOR Vd, Vn
<some complicated math>
```
The initial XOR means that they can be treated as commutative, removing
some of the unnecessary mov's introduced during register allocation.
Commit: d1538c15f9c65a70f4650bd724972536f00f5094
https://github.com/llvm/llvm-project/commit/d1538c15f9c65a70f4650bd724972536f00f5094
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
Revert fuzzer windows changes (#83551)
Commit: 8511b320807085e88a10ae7275c2255da9d0172a
https://github.com/llvm/llvm-project/commit/8511b320807085e88a10ae7275c2255da9d0172a
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
Log Message:
-----------
[clang] Remove unused lambda capture. (#83550)
Fixes the `sanitizer-x86_64-linux-android` buildbot.
Commit: 0e9a102129c07d31dccec06cb45f6e2a74c6e590
https://github.com/llvm/llvm-project/commit/0e9a102129c07d31dccec06cb45f6e2a74c6e590
Author: David Green <david.green at arm.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Remove unused AArch64ISD::BIT. NFC
These were last used in the fcopysign lowering, which now uses AArch64ISD::BSP.
Commit: 2d98d763a8e627b2d1a18a9cdd1c62a4b58be3aa
https://github.com/llvm/llvm-project/commit/2d98d763a8e627b2d1a18a9cdd1c62a4b58be3aa
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
Log Message:
-----------
[SLP]Fix the cost model for extracts combined with later shuffle.
If the buildvector node contains extract, which later should be combined
with some other nodes by shuffling, need to estimate the cost of this
shuffle before building the mask after shuffle.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/83442
Commit: 7ac03e8a369d8ac74a2c4d97a9e2a41221428abd
https://github.com/llvm/llvm-project/commit/7ac03e8a369d8ac74a2c4d97a9e2a41221428abd
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/ops.mlir
A mlir/test/Target/Cpp/bitwise_operators.mlir
Log Message:
-----------
[mlir][EmitC] Add bitwise operators (#83387)
This adds operations for bitwise operators. Furthermore, an UnaryOp
class and a helper to print unary operations are introduced.
Commit: 0baf4ba362917b6bde127668a6ffa21213f42325
https://github.com/llvm/llvm-project/commit/0baf4ba362917b6bde127668a6ffa21213f42325
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-03-01 (Fri, 01 Mar 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Context.h
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/InstallAPI/Frontend.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/stream-note.c
M clang/test/CodeGen/PowerPC/aix-tls-model.cpp
M clang/test/CodeGen/aarch64-cpu-supports.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/aix-attr-tls_model.c
M clang/test/Sema/builtin-cpu-supports.c
M clang/unittests/Analysis/FlowSensitive/TestingSupport.h
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.h
M compiler-rt/lib/sanitizer_common/sanitizer_procmaps_bsd.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/test/HLFIR/all-lowering.fir
M flang/test/HLFIR/any-lowering.fir
M flang/test/HLFIR/count-lowering-default-int-kinds.fir
M flang/test/HLFIR/count-lowering.fir
M flang/test/HLFIR/dot_product-lowering.fir
M flang/test/HLFIR/extents-of-shape-of.f90
M flang/test/HLFIR/matmul-lowering.fir
M flang/test/HLFIR/maxloc-lowering.fir
M flang/test/HLFIR/maxval-lowering.fir
M flang/test/HLFIR/minloc-lowering.fir
M flang/test/HLFIR/minval-lowering.fir
M flang/test/HLFIR/mul_transpose.f90
M flang/test/HLFIR/product-lowering.fir
M flang/test/HLFIR/sum-lowering.fir
M flang/test/HLFIR/transpose-lowering.fir
M flang/test/Lower/convert.f90
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/include/llvm-libc-macros/float-macros.h
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lldb/include/lldb/Core/Progress.h
M lldb/test/API/lang/c/local_variables/TestLocalVariables.py
M lldb/test/CMakeLists.txt
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/RNBRemote.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/MC/MCExpr.h
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/include/llvm/TextAPI/Record.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/XCOFFObjectWriter.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/lib/TextAPI/RecordVisitor.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/aes.ll
M llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.mir
M llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
A llvm/test/CodeGen/PowerPC/aix-tls-ld-xcoff-reloc-large.ll
A llvm/test/CodeGen/PowerPC/aix-tls-local-dynamic.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
M llvm/test/CodeGen/PowerPC/expand-isel-to-branch.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
M llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
M llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
M llvm/test/CodeGen/PowerPC/funnel-shift.ll
M llvm/test/CodeGen/PowerPC/i1-to-double.ll
M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/pr43976.ll
M llvm/test/CodeGen/PowerPC/pr49509.ll
M llvm/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll
M llvm/test/CodeGen/PowerPC/select-cc-no-isel.ll
M llvm/test/CodeGen/PowerPC/select.ll
M llvm/test/CodeGen/PowerPC/select_const.ll
M llvm/test/CodeGen/PowerPC/smulfixsat.ll
M llvm/test/CodeGen/PowerPC/spe.ll
M llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/PowerPC/umulfixsat.ll
M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/PowerPC/varargs.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/X86/apx/compress-evex.mir
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
A llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out-no-ps.ll
A llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_loose.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul_slice.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir
A mlir/test/Target/Cpp/bitwise_operators.mlir
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/354c7adba6cd...0baf4ba36291
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