[all-commits] [llvm/llvm-project] 4f132d: [RISCV] Enable PostRAScheduler for SiFive7 (#83166)

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f132dca711f4b425f9d370f5d59efb766b8bffa
      https://github.com/llvm/llvm-project/commit/4f132dca711f4b425f9d370f5d59efb766b8bffa
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-02-29 (Thu, 29 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll

  Log Message:
  -----------
  [RISCV] Enable PostRAScheduler for SiFive7 (#83166)

Based on numbers collected in our downstream toolchain.



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