[all-commits] [llvm/llvm-project] dbca8a: [DAG] Improve known bits of Zext/Sext loads with r...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbca8a49b6dbbb79913d6a1bc1d59f4947353e96
      https://github.com/llvm/llvm-project/commit/dbca8a49b6dbbb79913d6a1bc1d59f4947353e96
  Author: David Green <david.green at arm.com>
  Date:   2024-02-29 (Thu, 29 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
    M llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

  Log Message:
  -----------
  [DAG] Improve known bits of Zext/Sext loads with range metadata (#80829)

This extends the known bits for extending loads which have range
metadata, handling the range metadata on the original memory type,
extending that to the correct BitWidth.



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