[all-commits] [llvm/llvm-project] 14d8c4: [RISCV] Add more intrinsics into canSplatOperand. ...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 14d8c4563e045fc3da82cb7268b1066cfd1bb6f0
      https://github.com/llvm/llvm-project/commit/14d8c4563e045fc3da82cb7268b1066cfd1bb6f0
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2024-02-29 (Thu, 29 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

  Log Message:
  -----------
  [RISCV] Add more intrinsics into canSplatOperand. (#83106)

This patch adds smin/smax/umin/umax/sadd_sat/ssub_sat/uadd_sat/usub_sat
into canSplatOperand. It can help llvm fold vv instructions with one
splat operand to vx instructions.



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