[all-commits] [llvm/llvm-project] 41427b: [AArch64] Disable FastISel/GlobalISel for ZT0 stat...
Sander de Smalen via All-commits
all-commits at lists.llvm.org
Wed Feb 28 02:42:28 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 41427b0e8eeed9891d4e98ea9ac6a812682fd507
https://github.com/llvm/llvm-project/commit/41427b0e8eeed9891d4e98ea9ac6a812682fd507
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-28 (Wed, 28 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
Log Message:
-----------
[AArch64] Disable FastISel/GlobalISel for ZT0 state (#82768)
For __arm_new("zt0") we need to have special setup code in the prologue.
For calls that don't preserve zt0, we need to emit code preserve ZT0
around the call.
This is only emitted by SelectionDAG ISel at the moment.
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