[all-commits] [llvm/llvm-project] 9617da: [RISCV] Use a ta vslideup if inserting over end of...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9617da88ab961145047076c45bb2bb1ac4513634
      https://github.com/llvm/llvm-project/commit/9617da88ab961145047076c45bb2bb1ac4513634
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-02-28 (Wed, 28 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

  Log Message:
  -----------
  [RISCV] Use a ta vslideup if inserting over end of InterSubVT (#83230)

The description in #83146 is slightly inaccurate: it relaxes a tail
undisturbed vslideup to tail agnostic if we are inserting over the
entire tail of the vector **and** we didn't shrink the LMUL of the
vector being inserted into.

This handles the case where we did shrink down the LMUL via InterSubVT
by checking if we inserted over the entire tail of InterSubVT, the
actual type that we're performing the vslideup on, not VecVT.



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