[all-commits] [llvm/llvm-project] f42e32: [AArch64] Use FMOVDr for clearing upper bits (#83107)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f42e321b9fb54300c4450e699cd3cc453e994b58
      https://github.com/llvm/llvm-project/commit/f42e321b9fb54300c4450e699cd3cc453e994b58
  Author: David Green <david.green at arm.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64] Use FMOVDr for clearing upper bits (#83107)

This adds some tablegen patterns for generating FMOVDr from concat(X,
zeroes), as the FMOV will implicitly zero the upper bits of the
register. An extra AArch64MIPeepholeOpt is needed to make sure we can
remove the FMOV in the same way we would remove the insert code.



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