[all-commits] [llvm/llvm-project] f7cf1f: [CodeGen][MISched] dumpSched direction depends on ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7cf1f6236ee299d65c2b33429c1d3b729f54c32
      https://github.com/llvm/llvm-project/commit/f7cf1f6236ee299d65c2b33429c1d3b729f54c32
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
    M llvm/lib/CodeGen/MachineScheduler.cpp

  Log Message:
  -----------
  [CodeGen][MISched] dumpSched direction depends on field in DAG.

This is a precommit to supporting post reg-alloc bottom up scheduling.
We'd like to have post-ra scheduling direction that can be different from
pre-ra direction. The current dumpSchedule function is changed in this
patch to support the fact that the post-ra and pre-ra directions will
depend on different command line options.


  Commit: 9106b58ce4e8dada167eec50178a9e154342e4ba
      https://github.com/llvm/llvm-project/commit/9106b58ce4e8dada167eec50178a9e154342e4ba
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/lib/CodeGen/MachineScheduler.cpp
    A llvm/test/CodeGen/RISCV/misched-postra-direction.mir

  Log Message:
  -----------
  [CodeGen][MISched] Add misched post-regalloc bottom-up scheduling

There is the possibility that the bottom-up direction will lead to
performance improvements on certain targets, as this is certainly the case for
the pre-regalloc GenericScheduler. This patch will give people the
opportunity to experiment for their sub-targets. However, this patch
keeps the top-down approach as the default for the PostGenericScheduler
since that is what subtargets expect today.


Compare: https://github.com/llvm/llvm-project/compare/c95febcb4008...9106b58ce4e8

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