[all-commits] [llvm/llvm-project] e7900e: AMDGPU: Regenerate baseline mir tests

Matt Arsenault via All-commits all-commits at lists.llvm.org
Mon Feb 26 21:15:33 PST 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7900e695e7dfb36be8651d914a31f42a5d6c634
      https://github.com/llvm/llvm-project/commit/e7900e695e7dfb36be8651d914a31f42a5d6c634
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-02-27 (Tue, 27 Feb 2024)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
    M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
    M llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
    M llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
    M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
    M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
    M llvm/test/CodeGen/AMDGPU/commute-vop3.mir
    M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
    M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
    M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
    M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
    M llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir
    M llvm/test/CodeGen/AMDGPU/gws-hazards.mir
    M llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
    M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
    M llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
    M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
    M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
    M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
    M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
    M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
    M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
    M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
    M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir

  Log Message:
  -----------
  AMDGPU: Regenerate baseline mir tests



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