[all-commits] [llvm/llvm-project] b791a5: [CodeGenSchedule] Don't allow invalid ReadAdvances...

[Visoiu Mistrih Francis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b791a51730f145308f3607d0d33038af78138304
      https://github.com/llvm/llvm-project/commit/b791a51730f145308f3607d0d33038af78138304
  Author: Visoiu Mistrih Francis <890283+francisvm at users.noreply.github.com>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    A llvm/test/TableGen/ReadAdvanceInvalidWrite.td
    M llvm/test/tools/llvm-mca/AArch64/Exynos/float-divide-multiply.s
    M llvm/utils/TableGen/CodeGenSchedule.cpp
    M llvm/utils/TableGen/SubtargetEmitter.cpp

  Log Message:
  -----------
  [CodeGenSchedule] Don't allow invalid ReadAdvances to be formed (#82685)

Forming a `ReadAdvance` with an entry in the `ValidWrites` list that is
not used by any instruction results in the entire `ReadAdvance` to be
ignored by the scheduler due to an invalid entry.

The `SchedRW` collection code only picks up `SchedWrites` that are
reachable from `Instructions`, `InstRW`, `ItinRW` and `SchedAlias`,
leaving the unreachable ones with an invalid entry (0) in
`SubtargetEmitter::GenSchedClassTables` when going through the list of
`ReadAdvances`



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