[all-commits] [llvm/llvm-project] b4b76b: [AArch64] Make +pauth enabled in Armv8.3-a by defa...

Mon Feb 26 17:39:49 PST 2024

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: b4b76bdbf1dab6199e4112781f37e96f1902bfcd
      https://github.com/llvm/llvm-project/commit/b4b76bdbf1dab6199e4112781f37e96f1902bfcd
  Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/test/CodeGen/aarch64-targetattr.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M llvm/include/llvm/TargetParser/AArch64TargetParser.h
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)

Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.

After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.

The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.

(cherry picked from commit a52eea66795018550e95c4b060165a7250899298)

  Commit: 83283342c38e03fc501c84b9fad7cd62f1d629d3
      https://github.com/llvm/llvm-project/commit/83283342c38e03fc501c84b9fad7cd62f1d629d3
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M clang/test/Driver/aarch64-cssc.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/include/llvm/TargetParser/AArch64TargetParser.h
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/TargetParser/Host.cpp
    M llvm/test/CodeGen/AArch64/cpus.ll
    M llvm/test/CodeGen/AArch64/neon-dot-product.ll
    M llvm/test/CodeGen/AArch64/remat.ll
    M llvm/test/MC/AArch64/armv8.2a-dotprod.s
    M llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
    M llvm/unittests/TargetParser/Host.cpp
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.

Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.

(cherry picked from commit fbba818a78f591d89f25768ba31783714d526532)

  Commit: f1978d19a4ab28d0684d036973a50f65f1e08fae
      https://github.com/llvm/llvm-project/commit/f1978d19a4ab28d0684d036973a50f65f1e08fae
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    A llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkor.td
    M llvm/lib/Target/AArch64/AArch64SchedKryo.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s

  Log Message:
  -----------
  [AArch64] Initial Ampere1B scheduling model (#81341)

The Ampere1B core is enabled with a new scheduling/pipeline model, as it
provides significant updates over the Ampere1 core; it reduces latencies
on many instructions, has some micro-ops reassigned between the XY and X
units, and provides modelling for the instructions added since Ampere1
and Ampere1A.

As this is the first model implementing the CSSC instructions, we update
the UnsupportedFeatures on all other models (that have CompleteModel
set).

Testcases are added under llvm-mca: these showed the FullFP16 feature
missing, so we are adding it in as part of this commit.

This *adds tests and additional fixes* compared to the reverted #81338.

(cherry picked from commit dd1897c6cb028bda7d4d541d1bb33965eccf0a68)

  Commit: 6d8f9290b6afa5e61841124ae1bdeb96d9ada820
      https://github.com/llvm/llvm-project/commit/6d8f9290b6afa5e61841124ae1bdeb96d9ada820
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

  Log Message:
  -----------
  [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744)

One of the whitespace fixes didn't get added to the commit introducing
the Ampere1B model.
Clean it up.

(cherry picked from commit 3369e341288b3d9bb59827f9a2911ebf3d36408d)

Compare: https://github.com/llvm/llvm-project/compare/a7a74ece1d6b...6d8f9290b6af

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