[all-commits] [llvm/llvm-project] f1bb88: [RISCV] Use PromoteSetCCOperands to promote operan...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1bb88bee248fb30e3145a2a19373233b7a59882
      https://github.com/llvm/llvm-project/commit/f1bb88bee248fb30e3145a2a19373233b7a59882
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll

  Log Message:
  -----------
  [RISCV] Use PromoteSetCCOperands to promote operands for UMAX/UMIN during type legalization. (#82716)

For RISC-V, we were always choosing to sign extend when promoting
i32->i64. If the promoted inputs happen to be zero extended already, we
should use zero extend instead. This is what we do for SETCC.



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