[all-commits] [llvm/llvm-project] 433f8e: MachineSSAUpdater: use all vreg attributes instead...

[Petar Avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 433f8e741e7d4a5b7dad3e078dd847efa6afee5e
      https://github.com/llvm/llvm-project/commit/433f8e741e7d4a5b7dad3e078dd847efa6afee5e
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineSSAUpdater.h
    M llvm/lib/CodeGen/MachineSSAUpdater.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

  Log Message:
  -----------
  MachineSSAUpdater: use all vreg attributes instead of reg class only (#78431)

When initializing MachineSSAUpdater save all attributes of current
virtual register and create new virtual registers with same attributes.
Now new virtual registers have same both register class or bank and LLT.
Previously new virtual registers had same register class but LLT was not
set (LLT was set to default/empty LLT).
Required by GlobalISel for AMDGPU, new 'lane mask' virtual registers
created by MachineSSAUpdater need to have both register class and LLT.

patch 4 from: https://github.com/llvm/llvm-project/pull/73337



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