[all-commits] [llvm/llvm-project] 8cfb71: [mlir][ArmSME] Replace use of `isa` with `isa_and_...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8cfb71613c452dd45a84a74affe8464bfd33de02
      https://github.com/llvm/llvm-project/commit/8cfb71613c452dd45a84a74affe8464bfd33de02
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-02-26 (Mon, 26 Feb 2024)

  Changed paths:
    M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
    M mlir/test/Dialect/ArmSME/vector-legalization.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Replace use of `isa` with `isa_and_present` (#82798)

`op` can be null here, in which case this should just return a null
value back.



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